CY8C3245PVI-157 Cypress Semiconductor Corp, CY8C3245PVI-157 Datasheet - Page 26

• Manufacturer Part Number: CY8C3245PVI-157
• Description: CY8C3245PVI-157
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3245PVI-157

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Each SFR supported I/O port provides three SFRs:
5.7.3.1 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See
accessed using the EMIF. See
page 24.
Table 5-5. XDATA Data Address Map
Document Number: 001-56955 Rev. *J
0×00 0000 – 0×00 1FFF SRAM
0×00 4000 – 0×00 42FF
0×00 4300 – 0×00 43FF
0×00 4400 – 0×00 44FF
0×00 4500 – 0×00 45FF
0×00 4700 – 0×00 47FF
0×00 4900 – 0×00 49FF
0×00 4E00 – 0×00 4EFF Decimator
0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs
0×00 5000 – 0×00 51FF
0×00 5400 – 0×00 54FF
0×00 5800 – 0×00 5FFF Analog Subsystem interface
0×00 6000 – 0×00 60FF
0×00 6400 – 0×00 6FFF UDB configuration
0×00 7000 – 0×00 7FFF PHUB configuration
0×00 8000 – 0×00 8FFF EEPROM
SFRPRTxDR sets the output data state of the port (where x is
port number and includes ports 0 – 6, 12 and 15).
The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
Table
Address Range
5-5. External, that is, off-chip, memory can be
I/O System and Routing
Clocking, PLLs, and oscillators
Power management
Interrupt controller
Ports interrupt control
Flash programming interface
I
I/O ports control
External Memory Interface (EMIF)
control registers
USB controller
2
C controller
External Memory Interface
Purpose
on page 34.
on
Table 5-5. XDATA Data Address Map (continued)
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 50 MHz clock, accurate to ±1 percent over
voltage and temperature. Additional internal and external clock
sources allow each design to optimize accuracy, power, and
cost. All of the system clock sources can be used to generate
other clock frequencies in the 16-bit clock dividers and UDBs for
anything the user wants, for example a UART baud rate
generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent PSoC.
Key features of the clocking system include:
0×01 0000 – 0×01 FFFF Digital Interconnect configuration
0×05 0220 – 0×05 02F0
0×08 0000 – 0×08 1FFF Flash ECC bytes
0×80 0000 – 0×FF FFFF External Memory Interface
Seven general purpose clock sources
IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
Independently sourced clock in all clock dividers
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the bus clock
Dedicated 4-bit divider for the CPU clock
Automatic clock configuration in PSoC Creator
3- to 24-MHz IMO, ±1 percent at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see
DSI signal from an external I/O pin or other logic
24- to 50- MHz fractional PLL sourced from IMO, MHzECO,
or DSI
Clock Doubler
1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
sleep timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
Address Range
PSoC
USB Clock Domain
Debug controller
®
3: CY8C32 Family
Purpose
on page 29
Data Sheet
Page 26 of 119
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