CY8C20121-SX1IT Cypress Semiconductor Corp, CY8C20121-SX1IT Datasheet

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CY8C20121-SX1IT

Manufacturer Part Number
CY8C20121-SX1IT
Description
CY8C20121-SX1IT
Manufacturer
Cypress Semiconductor Corp
Series
CapSense Express™ CY8C20xxxr
Datasheet

Specifications of CY8C20121-SX1IT

Controller Type
Capacitive Sensing Controller
Interface
I²C
Voltage - Supply
2.4 V ~ 5.25 V
Current - Supply
1.5mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Package Type
SOIC
Mounting
Surface Mount
Pin Count
8
Processor Series
CY8C201xx
Core
M8C
Program Memory Type
Flash
Interface Type
I2C
Operating Supply Voltage
2.4 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3218-CAPEXP1
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1. Features
Cypress Semiconductor Corporation
Document Number: 001-53516 Rev. *E
Capacitive button input tied to a configurable output
Target Applications
Industry's best configurability
Advanced features
Wide range of operating voltages
Robust sensing algorithm
High sensitivity, low noise
Immunity to RF and AC noise
Low radiated EMC noise
Supports wide range of input capacitance, sensor shapes,
and sizes
Printers
Cellular handsets
LCD monitors
Portable DVD players
Custom sensor tuning
Output supports strong 20 mA sink current
Output state can be controlled through I
CapSense input state
Run time reconfigurable over I
Plug-and-play with factory defaults – tuned to support up to
1 mm overlay
Nonvolatile storage of custom settings
Easy integration into existing products – configure output to
match system
No external components required
World class free configuration tool
2.45 V to 2.9 V
3.10 V to 3.6 V
4.75 V to 5.25 V
2
C
2
C or directly from
CapSense
198 Champion Court
Two Button Capacitive Controllers
2. Overview
The CapSense
sensing (CapSense) buttons and two general purpose outputs in
CY8C20121 and one CapSense button and one general
purpose output in CY8C20111. The device functionality is
configured through the I
nonvolatile memory for automatic loading at power on. The
digital outputs are controlled from CapSense inputs in factory
default settings, but are user configurable for direct control
through I
The four key blocks that make up the CY8C20111 and
CY8C20121 controllers are: a robust capacitive sensing core
with high immunity against radiated and conductive noise,
control registers with nonvolatile storage, configurable outputs,
and I
parameters needed to adjust the operation and sensitivity of the
CapSense buttons and outputs and permanently store the
settings. The standard I
the host to configure the device and read sensor information in
real time. I
hardware strapping.
®
I
Industrial temperature range: –40 °C to +85 °C
Available in 8-Pin SOIC package
2
C communication
Supported from 1.8 V
Internal pull-up resistor support option
Data rate up to 400 kbps.
Configurable I
Express™ – One Button and
2
C communications. The user can configure registers with
2
C.
2
C address is fully configurable without any external
San Jose
®
Express™ controllers support two capacitive
2
C addressing
,
CY8C20111, CY8C20121
CA 95134-1709
2
2
C serial communication interface allows
C port and can be stored in on-board
Revised November 19, 2010
408-943-2600
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Related parts for CY8C20121-SX1IT

CY8C20121-SX1IT Summary of contents

Page 1

... Overview ® The CapSense sensing (CapSense) buttons and two general purpose outputs in CY8C20121 and one CapSense button and one general purpose output in CY8C20111. The device functionality is configured through the I nonvolatile memory for automatic loading at power on. The digital outputs are controlled from CapSense inputs in factory ...

Page 2

... CS_NEG_NOISE_TH ................................................ 16 CS_LOW_BL_RST .................................................... 16 CS_FILTERING ......................................................... 17 CS_SCAN_POS_x .................................................... 17 CS_FINGER_TH_x ................................................... 18 CS_IDAC_x ............................................................... 18 I2C_ADDR_LOCK ..................................................... 18 DEVICE_ID ............................................................... 19 DEVICE_STATUS ..................................................... 19 I2C_ADDR_DM ......................................................... 20 Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 CS_READ_BUTTON ................................................. 20 CS_READ_BLx ......................................................... 21 CS_READ_DIFFx ...................................................... 21 CS_READ_RAWx ..................................................... 21 CS_READ_STATUS ................................................. 22 COMMAND_REG ...................................................... 22 Layout Guidelines and Best Practices ......................... 24 Example PCB Layout Design with Two CapSense Buttons and Two LEDs .................... 26 Operating Voltages ......................................................... 27 CapSense Constraints ................................................... 27 Electrical Specifications ...

Page 3

... I2C SDA I C Data 4 CS0 CapSense Input Connect 6 DIG0 Digital Output Connect 8 V Supply Voltage DD Figure 2. CY8C20121 Pin Diagram – 8 SOIC- 2 Button Table 2. Pin Definitions – 8 SOIC- 2 Button Pin No Name 1 V Ground I2C SCL I C Clock 2 3 I2C SDA I C Data 4 ...

Page 4

... Typical Circuits 5.1 Circuit-1: One Button and One LED   5.2 Circuit-2: One Button and One LED with I   Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev Interface CY8C20111, CY8C20121 Page [+] Feedback ...

Page 5

... Circuit-3: Two Buttons and Two LEDs with I   5.4 Circuit-4: Compatibility with 1   Note 2. 1.8 V ≤ V _I2C ≤ V _CE and 2.4 V ≤ V _CE ≤ 5. Document Number: 001-53516 Rev Interface 2 [2] C Signaling CY8C20111, CY8C20121 Page [+] Feedback ...

Page 6

... Zero in the LSb indicates the write transaction form master and one indicates read transfer by the master. Table 3 shows example for different CY8C20111, CY8C20121 I2C Pull UPs I2C BUS 2 C data 2 C addresses Bit Slave Address (in Hex) 0(W) 02 1(R) 03 0(W) 96 1(W) 97 Page [+] Feedback ...

Page 7

... Figure 3. Write ACK Time Representation Figure 4. Read ACK Time Representation A Data A Data A A Stop A Data Data CY8C20111, CY8C20121 2 C Master) must wait for a specific amount of Format for Register Write 2 C master initiates any data transfer with on page Data A Stop N Stop Page ...

Page 8

... Notes 3. These registers are writable only after entering into setup mode. All other registers are available for read and write in normal and setup mode. 4. These registers are available only in CY8C20121 device. 5. The Ack times specified are 1x I2C Ack times. Document Number: 001-53516 Rev. *E ...

Page 9

... Start scan Stop scan Get CapSense scan status Note 6. ‘W’ indicates the write transfer. The next byte of data represents the 7 bit I Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Executable Duration the Device is NOT Ac- Mode cessible after ACK (in ms) Setup/Normal Setup/Normal Setup/Normal ...

Page 10

... Used to represent the output status 0 Output low 1 Output high Description A bit set in this register sets the logic level of the output. 0 Logic ‘0’ 1 Logic ‘1’ CY8C20111, CY8C20121 1 0 R:01 STS[ R:03 STS[1: W:01 DIG[ W:03 DIG[1: RW:01 CS[ RW:03 CS[1:0] Page [+] Feedback ...

Page 11

... These bits are used to enable DIG outputs. 0 Disable DIG output 1 Enable DIG output Description These bits are used to set the strong drive mode to DIG outputs. 0 Strong drive mode not set 1 Strong drive mode set CY8C20111, CY8C20121 1 0 RW:01 DIG[ RW:03 DIG [1: RW: RW:03 DM [1:0] Page [+] Feedback ...

Page 12

... OP_SEL_0 [0] LOGICAL_OPR_INPUTx [0] ENB CS0 LOGICAL_OPR_INPUTx [1] ENB CS1 INPUT SELECTION LOGIC Document Number: 001-53516 Rev. *E Figure 5. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] INVERSION LOGIC OP_SEL_0 [1] Figure 6. CY8C20121 Digital Logic Diagram A AND / OR Logic selection B S OP_SEL_x [0] CY8C20111, CY8C20121 A DIG0 AND / OR Logic selection B S OP_SEL_0 [7] ...

Page 13

... This bit selects which operator should be used to compute logic operation. 0 Logic operator OR is used on inputs 1 Logic operator AND is used on inputs Description These bits selects the input for logic operation block. CY8C20111, CY8C20121 1 0 RW: 0 RW: 0 InvOp Operator 1 0 RW:01 CSL[ RW:01 CSL [1: RW:02 CSL [1:0] ...

Page 14

... These bits are used to set the noise threshold value RW:64 BLUT[7:0] Description These bits set the threshold that the bucket must reach for baseline to increment RW:A0 STLNG_TM[7:0] Description These bits are used to set the settling time value. CY8C20111, CY8C20121 Page [+] Feedback ...

Page 15

... These bits selects the CapSense clock. CS_CLK[1:0] Frequency of Operation 00 IMO 01 IMO/2 10 IMO/4 11 IMO/8 This bit is used to enable or disable sensor auto reset. 0 Disable Sensor auto reset 1 Enable Sensor auto reset RW:0A HYS[7:0] Description These bits are used to set the hysteresis value. CY8C20111, CY8C20121 Page [+] Feedback ...

Page 16

... RW:0A DB[7:0] Description These bits are used to set the debounce value RW:0A NNT[7:0] Description These bits are used to set the negative noise value RW:0A LBR[7:0] Description These bits are used to set the Low Baseline Reset value. CY8C20111, CY8C20121 Page [+] Feedback ...

Page 17

... This bit enables average filter on raw counts. 0 Disable the average filter 1 Enable the average filter These bits are used to select the number of CapSense samples to average: Avg_Order[1:0] in Hex Description This bit sets the scan position. CY8C20111, CY8C20121 RW: 00 Avg_Order[1: communication Samples to Average RW: 0 Scan_Pstn 2 ...

Page 18

... These bit set the finger threshold for CapSense inputs RW: 0A IDAC[7:0] Description These bit set the IDAC values address register (7Ch) access. The device I Description This bit gives the lock/unlock status Unlocked 1 Locked CY8C20111, CY8C20121 WPR: 0 I2CAL 2 C address should be modified by writing 2 C address. Page [+] Feedback ...

Page 19

... Store or Write POR command. This bit indicates whether CapSense function is enabled or disabled. 0 Functionality of CapSense block is disabled 1 Functionality of CapSense block is enabled This bit indicates whether GP Output function is enabled or disabled. 0 Functionality of Digital output block is disabled 1 Functionality of Digital output block is enabled CY8C20111, CY8C20121 ...

Page 20

... Enable CapSense scan result reading These bits decide which CapSense button scan result are read. When writing to this register, the bitmask must contain only one bit set to ’1’, otherwise the data is discarded. CSBN [1:0] CapSense Button CY8C20111, CY8C20121 RW: 0 CSBN[0] 2 ...

Page 21

... Reading from this register returns the 2-byte current raw count value for the selected CapSense input. Bit Name 7:0 RC [7:0] Document Number: 001-53516 Rev [7:0] Description These bits represent the baseline value DIF [7:0] Description These bits represent the sensor difference count [7:0] Description These bits represent the raw count value. CY8C20111, CY8C20121 Page [+] Feedback ...

Page 22

... ACK and the data is NOT saved to flash. To define new POR defaults: ■ Write command 03h ■ Write 122 data bytes with new values of registers (use the _flash.iic file generated from s/w tool) ■ Write one CRC byte calculated as XOR of previous 122 data bytes CY8C20111, CY8C20121 BT_ST[ ...

Page 23

... A0h register, reading one byte returns the CSA scanning status. It returns the LVD_STOP_SCAN and STOP_SCAN bits. LVD_STOP_SCAN is bit 3 - Set when CSA is stopped because V operating range. STOP_SCAN is bit 2 - Set when CSA is stopped by the user by writing command 0x0A. CY8C20111, CY8C20121 operating range outside the valid ...

Page 24

... Cut a hole in the sensor pad and use rear mountable LEDs. Refer Example PCB Layout Design with Two CapSense Buttons and Two LEDs Standard board thickness for CapSense FR4 based designs is 1.6 mm. CY8C20111, CY8C20121 Recommendations/Remarks on page 26. Page [+] Feedback ...

Page 25

... X: Button to ground clearance Y: Button to button clearance   Document Number: 001-53516 Rev. *E Figure 7. Button Shapes Figure 8. Button Layout Design Figure 9. Recommended Via-hole Placement CY8C20111, CY8C20121 Page [+] Feedback ...

Page 26

... Example PCB Layout Design with Two CapSense Buttons and Two LEDs     Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Figure 10. Top Layer Figure 11. Bottom Layer Page [+] Feedback ...

Page 27

... CapSense Sensor Overlay Thickness Supply Voltage Variation ( Document Number: 001-53516 Rev page 7 and CapSense Express Commands Min Typ Max Units All layout best practices followed, properly tuned and noise free condition. ± 5% CY8C20111, CY8C20121 on page 8. I2C 4x Ack time is Notes Page [+] Feedback ...

Page 28

... V Human body model ESD – – 200 mA Min Typ Max Unit –40 – +85 °C –40 – +100 °C Min Typ Max Unit 2.40 – 5.25 V – 1.5 2.5 mA Conditions are V CY8C20111, CY8C20121 Notes Notes Notes = 3. ° Page [+] Feedback ...

Page 29

... V < 85 ° 2.90 V and –40 °C < Min Typ Max [7] 2.7 – – – 50,000 – – 10 – – CY8C20111, CY8C20121 Notes ≤ 10 µA/pin, V ≥ 3. ≥ 3. mA/pin mA/pin, V > 3.10 V, maximum sink current ≥ 3 ≥ 3.1 V, maximum sink current ...

Page 30

... The device automatically reconfigures itself to work in 3.3 V mode of operation. < 2.4 V The device goes into reset. < 4.73 V The scanning for CapSense parameters shuts down until the voltage returns to over 4.73 V. CY8C20111, CY8C20121 < 85 °C, respectively. Typical A Units Notes 2.4 V ≤ V ≤ 3.6 V ...

Page 31

... LOW period of the SCL clock LOWI2C t HIGH period of the SCL clock HIGHI2C t Setup time for a repeated START condition SUSTAI2C Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Min Typ Max Units Notes kHz Calculations during sleep operations are done based on ILO frequency ...

Page 32

... Min Max Min Max 0 – 0 – 250 – 100 – 4.0 – 0.6 – 4.7 – 1.3 – – – SUSTAI2C T HDDATI2C Sr Repeated START Condition CY8C20111, CY8C20121 Units Notes µs ns µs µ Bus T SPI2C T BUFI2C T SUSTOI2C P S STOP Condition Page [+] Feedback ...

Page 33

... Select CapSense button for reading scan result Set the read point to 82h Consecutive 6 reads gets baseline, difference count and RD RD raw count (all two byte each Set the read pointer Reading a byte gets status CapSense inputs CY8C20111, CY8C20121 Comment Page [+] Feedback ...

Page 34

... Diagram CY8C20111-SX1I 51-85066 8 SOIC CY8C20111-SX1IT 51-85066 8 SOIC (Tape and Reel) CY8C20121-SX1I 51-85066 8 SOIC CY8C20121-SX1IT 51-85066 8 SOIC (Tape and Reel) Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). 16.1 Ordering Code Definitions - 201 Tape and Reel ...

Page 35

... Package Diagram Document Number: 001-53516 Rev. *E Figure 13. 8-Pin (150-Mil) SOIC (51-85066) CY8C20111, CY8C20121 51-85066 *D Page [+] Feedback ...

Page 36

... Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Acronym Description ...

Page 37

... The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Page [+] Feedback ...

Page 38

... I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Page [+] Feedback ...

Page 39

... PCB design (both being computer generated files) and may also involve pin names. Document Number: 001-53516 Rev. *E and provides an interrupt to the system when V DD CY8C20111, CY8C20121 falls lower than a selected threshold. DD Page [+] Feedback ...

Page 40

... A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal system whose operation is synchronized by a clock signal. Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 ® registered trademark and Programmable System-on-Chip™ trademark Page [+] Feedback ...

Page 41

... A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 3 name for a power net meaning "voltage source." The most negative power supply signal. SS watchdog timer A timer that must be serviced periodically not serviced, the CPU resets after a specified period of time. Document Number: 001-53516 Rev. *E CY8C20111, CY8C20121 Page [+] Feedback ...

Page 42

... Document History Page Document Title: CY8C20111, CY8C20121 CapSense Document Number: 001-53516 Orig. of Rev. ECN No. Change ** 2709248 SLAN/PYRS *A 2821828 SSHH/FSU *B 2868929 SLAN *C 2892629 NJF *D 3043236 ARVM *E 3087790 NJF Document Number: 001-53516 Rev. *E ® Express™ - One Button and Two Button Capacitive Controllers ...

Page 43

... Revised November 19, 2010 2 C components from Cypress or one of its sublicensed Associated Companies conveys a license under the 2 C Standard Specification as defined by Philips. All products and company names CY8C20111, CY8C20121 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | ...

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