CY7C145-15AXC Cypress Semiconductor Corp, CY7C145-15AXC Datasheet
CY7C145-15AXC
Specifications of CY7C145-15AXC
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CY7C145-15AXC Summary of contents
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... Document #: 38-06034 Rev 8/9 Dual-Port Static RAM Functional Description The CY7C144 and CY7C145 are high speed CMOS and dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory ...
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... Interrupts ..................................................................... 5 Busy ............................................................................ 5 Master/Slave ............................................................... 5 Semaphore Operation ................................................. 5 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 Electrical Characteristics ................................................. 7 Electrical Characteristics ................................................. 8 Capacitance ...................................................................... 8 Document #: 38-06034 Rev. *H CY7C144 CY7C145 Switching Characteristics ................................................ 9 Switching Waveforms .................................................... 11 Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions and Legal Information ....................... 23 Worldwide Sales and Design Support ...
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... Document #: 38-06034 Rev. *H Figure 2. 64-Pin TQFP (Top View GND 5 INT BUSY GND M/S GND 9 BUSY INT Figure 3. 80-Pin TQFP (Top View CY7C145 CY7C144 CY7C145 INT L 42 BUSY GND CY7C144 41 M BUSY 38 INT INT 53 L BUSY 52 L GND 51 M/S 50 BUSY 49 R INT Page [+] Feedback ...
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... Master or Slave select V Power CC GND Ground Document #: 38-06034 Rev. *H 7C144-15 7C144-25 7C145- 220 180 60 40 Description is set when right port writes location 1FFE and is cleared when left port reads location L CY7C144 CY7C145 7C144-55 Unit 55 ns 160 pin is used when writing 0 Page [+] Feedback ...
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... All Semaphores on both sides should have a one written into them at initialization after CE is taken BLC from both sides to assure that they are free when needed. CY7C144 CY7C145 before attempting to read the semaphore. SOP + t after the rising SWRD ...
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... Left port obtains semaphore port accessing semaphore address 1 0 Right port obtains semaphore port accessing semaphore 0 1 Left port obtains semaphore port accessing semaphore CY7C144 CY7C145 Operation Power-down Read data in semaphore I/O lines disabled Write to semaphore Read Write Illegal condition Right Port R INT 012 ...
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... CC [ < 0 One port Commercial > V – 0 Industrial V > V – 0 < 0.2 V, Active IN [5] Port outputs MAX CY7C144 CY7C145 Ambient Temperature V CC 10 +70 C 10 +85 C 7C144-15 7C144-25 7C145-15 Unit Min Max Min Max ...
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... Figure 4. AC Test Loads and Waveforms = 250 Output C = 30pF (b) Th évenin Equivalent (Load 1) All Input Pulses 3.0 V 90% 90% 10% 10% GND CY7C144 CY7C145 7C144-55 Min Max 2.4 0.4 2.2 0.8 10 +10 10 +10 Commercial 160 ...
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... HZCE LZCE HZOE LZOE CY7C144 CY7C145 7C144-55 Unit Min Max ...
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... Semaphore Timing t SEM flag update pulse (OE or SEM) SOP t SEM flag write to read time SWRD t SEM flag contention SPS window Note 12. Test conditions used are Load 2. Document #: 38-06034 Rev. *H CY7C144 CY7C145 7C144-15 7C144-25 7C145-15 Min Max Min Max ...
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... L, SEM = H when accessing RAM SEM = L when accessing semaphores. L 17. BUSY = HIGH for the writing port. 18 LOW Document #: 38-06034 Rev ACE t DOE Data Valid t WC Match t PWE t SD Valid Match t WDD CY7C144 CY7C145 [13, 14] Data Valid [13, 15, 16] t HZCE t HZOE t PD [17, 18 DDD Valid Page [+] Feedback ...
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... Data I/O pins enter high impedance when OE is held LOW during write. Document #: 38-06034 Rev SCE PWE t SD Data Valid High Impedance SCE PWE Data Valid t HZWE High Impedance allow the I/O drivers to turn off and data to be PWE HZWE SD CY7C144 CY7C145 [19, 20, 21 LZOE [19, 21, 22 LZWE Page [+] Feedback ...
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... SPS Document #: 38-06034 Rev Valid Address SCE SOP t SD Data Valid PWE t SWRD t SOP Cycle Read Cycle [24, 25, 26] Figure 11. Semaphore Contention Match t SPS Match = CE = HIGH L CY7C144 CY7C145 [23] t OHA t ACE Data Valid OUT t DOE Page [+] Feedback ...
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... R/W R Data Address L BUSY L Data OUTL Figure 13. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 27 LOW Document #: 38-06034 Rev. *H Figure 12. Read with BUSY (M/S=HIGH Match t PWE t SD Valid Match t BLA t WDD t PWE CY7C144 CY7C145 [27 BHA t BDD t DDD Valid Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06034 Rev. *H Address Match BLC Address Match BLC Address Mismatch t t BLA BHA Address Mismatch t t BLA BHA CY7C144 CY7C145 [28] t BHC t BHC [28] Page [+] Feedback ...
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... 30 depends on which enable pin (CE or R/W INS INR L Document #: 38-06034 Rev. *H Figure 16. Interrupt Timing Diagrams t WC Write 1FFF [29 [30] t [30] INR t WC Write 1FFE [29 [30] t [30] INR ) is asserted last. L CY7C144 CY7C145 t RC Read 1FFF t RC Read 1FFE Page [+] Feedback ...
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... Ambient Temperature (°C) Typical Access Time Change Vs. Output Loading 30.0 25.0 20.0 15 ° 200 400 600 800 1000 Capacitance (pF) CY7C144 CY7C145 Output Source Current Vs. Output Voltage 200 160 120 ° 125 0 1.0 2.0 3.0 4.0 Output Voltage (V) Output Sink Current Vs ...
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... Speed (ns) Ordering Code 15 CY7C144-15AXC CY7C144-15JXI CY7C144-15AXI 25 CY7C144-25AXC 55 CY7C144-55AXC CY7C144-55JXC 8 K × 9 Dual-Port SRAM 15 CY7C145-15AXC Ordering Code Definitions CY7C 14X - Document #: 38-06034 Rev. *H Package Diagram Package Type 51-85046 64-pin Thin Quad Flat Pack (Pb-free) 51-85005 68-pin Plastic Leaded Chip Carrier (Pb-free) 51-85046 ...
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... Package Diagrams Figure 18. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85046 Document #: 38-06034 Rev. *H CY7C144 CY7C145 51-85046 *D Page [+] Feedback ...
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... Package Diagrams (continued) Figure 19. 80-Pin Thin Plastic Quad Flat Pack, 51-85065 Figure 20. 68-Pin Plastic Leaded Chip Carrier, 51-85005 Document #: 38-06034 Rev. *H CY7C144 CY7C145 51-85065 *C 51-85005 *B Page [+] Feedback ...
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... TQFP thin quad plastic flatpack I/O input/output SRAM static random access memory PLCC plastic leaded chip carrier TTL transistion transistor logic Document #: 38-06034 Rev. *H CY7C144 CY7C145 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...
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... See ECN Added Pb-free Logo Added Pb-free parts to ordering information: CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC, CY7C144-55AXC, CY7C144-55JXC, CY7C145-15AXC, CY7C145-35JXC 12/17/2008 Added CY7C144-15JXI in the Ordering information table 04/29/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams 03/22/2010 Updated Ordering Information Updated Package Diagrams ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06034 Rev. *H All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised December 2, 2010 CY7C144 CY7C145 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...