CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet - Page 8

• Manufacturer Part Number: CY7C1381D-133AXI
• Description: IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2147; CY7C1381D-133AXI

Switching Waveforms
Notes
Document #: 38-06037 Rev. *E
20. BUSY = HIGH for the writing port.
21. CE
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
24. R/W must be HIGH during all address transitions.
SEM OR CE
SEM OR CE
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
placed on the bus for the required t
be as short as the specified t
DATA OUT
ADDRESS
DATA OUT
ADDRESS
L
DATA IN
DATA IN
= CE
R/W
R/W
OE
R
= LOW.
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)
Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
PWE
.
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can
(continued)
t
SA
t
t
HZOE
SA
t
SCE
t
SCE
t
AW
t
HIGH IMPEDANCE
AW
t
HZWE
t
WC
t
WC
t
PWE
t
PWE
PWE
t
SD
DATA VALID
t
SD
or (t
HIGH IMPEDANCE
DATA VALID
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be
t
HD
t
t
HD
LZWE
t
HA
[22, 23, 24]
t
LZOE
[22, 24, 25]
t
CY7C138, CY7C139
HA
Page 8 of 17
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