CY7C1370DV25-167AXCT Cypress Semiconductor Corp, CY7C1370DV25-167AXCT Datasheet - Page 20
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CY7C1370DV25-167AXCT
Manufacturer Part Number
CY7C1370DV25-167AXCT
Description
CY7C1370DV25-167AXCT
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1370DV25-167AXI.pdf
(29 pages)
Specifications of CY7C1370DV25-167AXCT
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
167MHz
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1370DV25-167AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Over the Operating Range
Document Number: 38-05558 Rev. *H
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
Power
CYC
CH
CL
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
20. Timing reference 1.25 V when V
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
23. t
24. At any given voltage and temperature, t
25. This parameter is sampled and not 100% tested.
MAX
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
[22]
, t
CLZ
, t
EOLZ
, and t
V
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z
Clock to low Z
OE HIGH to output high Z
OE LOW to output low Z
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
WE, BW
ADV/LD set-up before CLK rise
Chip select set-up
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE, BW
ADV/LD hold after CLK rise
Chip select hold after CLK rise
EOHZ
CC
(typical) to the first access read or write
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[20, 21]
DDQ
x
x
set-up before CLK rise
hold after CLK rise
= 2.5 V.
EOHZ
[23, 24, 25]
[23, 24, 25]
Description
Power
is less than t
is the time power needs to be supplied above V
[23, 24, 25]
[23, 24, 25]
EOLZ
and t
CHZ
is less than t
CLZ
Min
4.0
1.7
1.7
1.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
1
–
–
–
–
–
0
to eliminate bus contention between SRAMs when sharing the same
–250
Max
250
DD
2.6
2.6
2.6
2.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
minimum initially, before a read or write operation can be
Min
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
5
–
–
–
–
–
0
–200
Max
200
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
2.2
2.2
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
CY7C1370DV25
CY7C1372DV25
1
6
–
–
–
–
–
0
–167
Max
167
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 20 of 29
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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