CY7C09579V-83AC Cypress Semiconductor Corp, CY7C09579V-83AC Datasheet - Page 21
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CY7C09579V-83AC
Manufacturer Part Number
CY7C09579V-83AC
Description
IC,SYNC SRAM,32KX36,CMOS,QFP,144PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09579V-100AXC.pdf
(32 pages)
Specifications of CY7C09579V-83AC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1.152M (32K x 36)
Speed
83MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C09579V-83AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Counter Reset (Flow-Through Outputs)
Notes
Document Number: 38-06054 Rev. *E
64. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
65. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
66. CE = B0 = B1 = B2 = B3 = V
67. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
CNTRST
Data
during a valid WRITE cycle.
Address
CNTEN
Address
Internal
Data
R/W
ADS
CLK
OUT
IN
A
t
SRST
X
t
HRST
t
CH2
IL
.
Counter
Reset
t
CYC2
(continued)
t
CL2
t
t
SD
SW
D
0
t
t
HD
HW
Address 0
[64, 65, 66, 67, 68]
Write
0
Address 0
t
CD1
Read
Q
0
Address 1
Read
t
SA
1
OUT
A
Q
n
1
should be in the High-Impedance state
t
HA
Address n
Read
A
A
n
n+1
CY7C09569V
CY7C09579V
Q
n
Page 21 of 32
A
n+1
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