CY7B933-JXIT Cypress Semiconductor Corp, CY7B933-JXIT Datasheet - Page 11

• Manufacturer Part Number: CY7B933-JXIT
• Description: CY7B933-JXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B933-JXIT

• Protocol: Fibre Channel
• Voltage - Supply: 4.5V ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The transmitter and receiver parallel interface timing and
functionality can be made to match the timing and functionality
of either an asynchronous FIFO or a clocked FIFO by appropri-
ately connecting signals (see
operation of the FIFO interface depends upon various
FIFO-specific access and response specifications.
The HOTLink transmitter and receiver serial interface provides a
seamless interface to various types of media. A minimal number
of external components are needed to properly terminate trans-
mission lines and provide PECL loads. For proper power supply
decoupling, a single 0.01 F for each device is all that is required
to bypass the V
a HOTLink transmitter and receiver interface to fiber-optic and
copper media. More information on interfacing HOTLink to
various media can be found in the
ations
Document #: 38-02017 Rev. *H
application note.
Q
SC/D,
RVS
CKR
RDY
07
RF
,
Q
SC/D,
RVS
CC
RDY
CKR
07
INX
and GND pins.
,
SERIAL DATA IN

DATA
RDY IS LOW FOR DATA
FALLING EDGE OF CKR
RF LATCHED ON
Figure 6 on page
DATA
Figure 4. CY7B933 Receiver Data Pipeline in Encoded Mode
Figure 7 on page 14
DATA
HOTLink Design Consider-
Figure 5. CY7B933 Framing Operation in Encoded Mode
DATA
RDY IS HIGH WHILE WAITING FOR K28.5
DATA
RDY IS HIGH IN FIELD OF K28.5S
12). Proper
RECEIVER LATENCY= 24 t
illustrates
K28.5
DATA
DATA BOUNDARY CHANGES
CY7B923 HOTLink Transmitter Operating
Mode Description
In normal operation, the transmitter can operate in either of two
modes. The encoded mode allows a user to send and receive
eight-bit data and control information without first converting it to
transmission characters. The bypass mode is used for systems
in which the encoding and decoding is performed in an external
protocol controller.
In either mode, data is loaded into the Input register of the Trans-
mitter on the rising edge of CKW. The input timing and functional
response of the Transmitter input can be made to match the
timing and functionality of either an asynchronous FIFO or a
clocked FIFO by an appropriate connection of input signals (see
Figure 6 on page
depends upon various FIFO-specific access and response
specifications.
CKR STRETCHES AS
B
DATA
+ 10 ns
RDY IS LOW FOR LAST K28.5
K28.5
12). Proper operation of the FIFO interface
RDY IS LOW
FOR K28.5
K28.5
CY7B923, CY7B933
DATA
DATA
RDY RESUMES
PARALLEL
DATA OUT
OPERATION
NORMAL
DATA
Page 11 of 40
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