CY62167ELL-45ZXIT Cypress Semiconductor Corp, CY62167ELL-45ZXIT Datasheet

CY62167ELL-45ZXIT

CY62167ELL-45ZXIT

Manufacturer Part Number
CY62167ELL-45ZXIT
Description
CY62167ELL-45ZXIT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62167ELL-45ZXIT

Format - Memory
RAM
Memory Type
SRAM
Memory Size
16M (2M x 8 or 1M x 16)
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP I
Density
16Mb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
21/20Bit
Package Type
TSOP-I
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
30mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Word Size
8/16Bit
Number Of Words
2M/1M
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16-Mbit (1M × 16 / 2M × 8) Static RAM
Features
Functional Description
The CY62167E is a high performance CMOS static RAM
organized as 1 M words by 16-bits/2 M words by 8-bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life™
(MoBL
The device also has an automatic power down feature that
Note
Cypress Semiconductor Corporation
Document Number: 001-15607 Rev. *B
Logic Block Diagram
1. For best practice recommendations, refer to the Cypress application note
Configurable as 1 M × 16 or as 2 M × 8 SRAM
Very high speed: 45 ns
Wide voltage range: 4.5 V to 5.5 V
Ultra low standby power
Ultra low active power
Easy memory expansion with CE
Automatic power-down when deselected
CMOS for optimum speed and power
Offered in 48-pin TSOP I package
Typical standby current: 1.5 µA
Maximum standby current: 12 µA
Typical active current: 2.2 mA at f = 1 MHz
®
POWER DOWN
) in portable applications such as cellular telephones.
CIRCUIT
A
A
A
A
A
A
A
A
A
A
A
[1]
10
9
8
7
6
5
4
3
2
1
0
1
, CE
2
CE
CE
BHE
BLE
, and OE features
2
1
198 Champion Court
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
COLUMN DECODER
1 M × 16 / 2 M × 8
DATA IN DRIVERS
RAM ARRAY
AN1064, SRAM System
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
(CE
input and output pins (I/O
impedance state when:
To write to the device, take chip enables (CE
HIGH) and write enable (WE) input LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
A
pins (I/O
the address pins (A
To read from the device, take chip enables (CE
HIGH) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
memory appears on I/O
page 11 for a complete description of read and write modes.
19
The device is deselected (CE
Outputs are disabled (OE HIGH)
Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH) or
A write operation is in progress (CE
LOW)
). If byte high enable (BHE) is LOW, then data from the I/O
1
HIGH, or CE
0
to I/O
8
through I/O
San Jose
Guidelines.
7
. If byte high enable (BHE) is LOW, then data from
2
LOW, or both BHE and BLE are HIGH). The
0
through A
,
15
CA 95134-1709
) is written into the location specified on
8
0
to I/O
through I/O
19
15
1
CY62167E MoBL
HIGH or CE
).
. See the
I/O
I/O
OE
BLE
BYTE
BHE
WE
1
0
8
LOW, CE
Revised August 16, 2010
15
–I/O
–I/O
) are placed in a high
0
“Truth Table”
7
15
through I/O
1
2
LOW and CE
LOW)
2
1
HIGH, and WE
LOW and CE
408-943-2600
CE
CE
2
1
0
7
through
on
), is
2
®
2
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CY62167ELL-45ZXIT Summary of contents

Page 1

... POWER DOWN CIRCUIT Note 1. For best practice recommendations, refer to the Cypress application note Cypress Semiconductor Corporation Document Number: 001-15607 Rev. *B 16-Mbit (1 M × × 8) Static RAM reduces power consumption by 99% when addresses are not toggling. Place the device into standby mode when deselected ...

Page 2

Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings............................................................. 4 Operating Range............................................................... 4 Electrical Characteristics................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance.......................................................... 4 AC Test Loads and Waveforms....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform................................................ 5 Switching ...

Page 3

... Product V Range (V) CC [4] Min Typ CY62167ELL 4.5 5.0 Notes 2. NC pins are not connected on the die. 3. The BYTE pin in the 48-TSOPI package must be tied × 8 SRAM by tying the BYTE signal the 2 M × 8 configuration, pin 45 is A20, while BHE, BLE and I ...

Page 4

... Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-15607 Rev input voltage Output current into outputs (LOW) ............................. 20 mA Static discharge voltage........................................... >2001 V (MIL-STD-883, method 3015) Latch-up current ...................................................... >200 mA Operating Range Device CY62167ELL Industrial –40 °C to +85 °C 4 5.5 V Test Conditions I = –1 2 ...

Page 5

AC Test Loads and Waveforms OUTPUT INCLUDING JIG AND SCOPE Parameters Data Retention Characteristics Over the operating range Parameter Description V V for data retention DR CC [13] ...

Page 6

Switching Characteristics Over the Operating Range [17, 18] Parameter READ CYCLE t Read cycle time RC t Address to data valid AA t Data hold from address change OHA t CE LOW and CE HIGH to data valid ACE 1 ...

Page 7

Switching Waveforms Figure 1. Read Cycle No. 1 (address transition controlled ADDRESS DATA OUT PREVIOUS DATA VALID Figure 2. Read Cycle No. 2 (OE controlled ADDRESS ACE BHE/BLE t LZBE OE t LZOE HIGH IMPEDANCE ...

Page 8

Switching Waveforms (continued) Figure 3. Write Cycle No. 1 (WE controlled ADDRESS BHE/BLE OE 28 NOTE DATA I/O t HZOE Notes 25. The internal write time of the memory is defined by the ...

Page 9

Switching Waveforms (continued) Figure 4. Write Cycle No. 2 (CE ADDRESS BHE/BLE OE 32 DATA I/O NOTE t HZOE Figure 5. Write Cycle No. 3 (WE controlled, OE LOW ADDRESS BHE/BLE ...

Page 10

Switching Waveforms (continued) Figure 6. Write Cycle No. 4 (BHE/BLE controlled, OE LOW ADDRESS BHE/BLE NOTE DATA I/O Notes 33 goes HIGH and CE goes LOW simultaneously with WE = ...

Page 11

Truth Table BHE 1 2 [35 [35 [35] [35 ...

Page 12

... Ordering Information Table 1 lists the CY62167ELL key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www ...

Page 13

Package Diagram Figure 7. 48-Pin TSOP I (12 mm × 18.4 mm × 1.0 mm), 51-85183 Document Number: 001-15607 Rev. *B ® CY62167E MoBL 51-85183 *B Page [+] Feedback ...

Page 14

Acronyms Acronym Description BHE byte high enable BLE byte low enable CMOS complementary metal oxide semiconductor CE chip enable I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package VFBGA very fine ball grid array ...

Page 15

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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