CY62147EV30LL-55ZSXET Cypress Semiconductor Corp, CY62147EV30LL-55ZSXET Datasheet - Page 8
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CY62147EV30LL-55ZSXET
Manufacturer Part Number
CY62147EV30LL-55ZSXET
Description
CY62147EV30LL-55ZSXET
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY62147EV30LL-45ZSXI.pdf
(16 pages)
Specifications of CY62147EV30LL-55ZSXET
Format - Memory
RAM
Memory Type
SRAM
Memory Size
4M (256K x 16)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Switching Waveforms
Document Number: 38-05440 Rev. *J
Notes
26. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE
27. The internal write time of the memory is defined by the overlap of WE, CE = V
28. Data I/O is high impedance if OE = V
29. If CE goes HIGH simultaneously with WE = V
30. During this period, the I/Os are in output state. Do not apply input signals.
ADDRESS
ADDRESS
and CE
of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
BHE/BLE
BHE/BLE
DATA I/O
DATA I/O
2
WE
WE
OE
OE
CE
CE
such that when CE
NOTE 30
NOTE 30
1
is LOW and CE
(continued)
IH
.
t
HZOE
t
SA
t
HZOE
Figure 8. Write Cycle No. 1: WE Controlled
Figure 9. Write Cycle No. 2: CE Controlled
2
IH
is HIGH, CE is LOW. For all other cases CE is HIGH.
, the output remains in a high impedance state.
t
SA
t
AW
t
AW
t
t
SCE
WC
t
IL
WC
, BHE, BLE, or both = V
t
BW
t
BW
DATA
t
t
PWE
SD
DATA
t
t
PWE
SD
t
IN
SCE
IN
IL
[26, 27, 28, 29]
[26, 27, 28, 29]
. All signals must be active to initiate a write and any
t
HD
t
CY62147EV30 MoBL
HA
t
HA
t
HD
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