CY25819SXCT Cypress Semiconductor Corp, CY25819SXCT Datasheet - Page 3

• Manufacturer Part Number: CY25819SXCT
• Description: IC,Miscellaneous Clock Generator,SOP,8PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock/Frequency Synthesizer, Fanout Distribution, Frequency Modulator, Spread Spectrum Clock Generatorr

Specifications of CY25819SXCT

• Pll: Yes
• Input: Clock, Crystal, Resonator
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 32MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 32MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3-Level Digital Inputs
S0 digital input is designed to sense three logic levels designated
as HIGH “1,” LOW “0,” and MIDDLE “M.” With this 3-Level digital
input logic, the 3-Level logic is able to detect three different logic
levels.
The S0 pin includes an on-chip 20K (10K/10K) resistor divider.
No external application resistors are needed to implement
3-Level logic, as follows.
Logic Level “0”: 3-Level logic pin connected to GND.
Logic Level “M”: 3-Level logic pin left floating (no connection.)
Logic Level “1”: 3-Level logic pin connected to Vdd.
Figure 1
Table 3. Modulation Rate Divider Ratios
Maximum Ratings
Supply Voltage (Vdd): .................................................. + 5.5V
Input Voltage Relative to Vdd: ..............................Vdd + 0.3V
Input Voltage Relative to Vss:............................... Vss + 0.3V
Operating Temperature:................................... 0°C to + 70°C
Storage Temperature: ................................ –65°C to + 150°C
Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, T
Document #: 38-07362 Rev. *C
Vdd
V
V
V
V
V
V
V
C
C
to V S S
Parameter
INH
INM
INL
OH1
OH2
OL1
OL2
S 0
IN1
IN2
L O W (0 )
L O G IC
CY25818
CY25819
Product
illustrates how to implement 3-Level Logic.
V S S
Power Supply Range
Input HIGH Voltage
Input MIDDLE Voltage
Input LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input Capacitance
Input Capacitance
Figure 1. 3-Level Logic
U N C O N N E C T E D
Description
M ID D L E (M )
S 0
L O G IC
[1, 2]
S0 Input
S0 Input
S0 Input
I
I
I
I
X
All Digital Inputs
Input Frequency Range
OH
OH
OL
OL
IN
to V D D
= 4 ma, SSCLK Output
= 10 ma, SSCLK Output
= 4 ma, SSCLK and REFCLK
= 6 ma, SSCLK and REFCLK
(Pin 1) and X
S 0
16–32 MHz
8–16 MHz
H IG H (H )
L O G IC
Conditions
V D D
OUT
A
(Pin 8)
= 0°C to +70°C and C
Modulation Rate
Spread Spectrum Clock Generators utilize frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (fmax) and minimum frequency
of the clock (fmin) determine this band of frequencies. The time
required to transition from fmin to fmax and back to fmin is the
period of the Modulation Rate, Tmod. The Modulation Rates of
SSCG clocks are generally referred to in terms of frequency, and
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine
the Modulation Rate.
In the case of CY25819 devices, the (Spread Spectrum)
Modulation Rate, fmod, is given by the following formula:
fmod = f
where fmod is the Modulation Rate, f
and DR is the Divider Ratio, as given in
IN
/DR
0.85 Vdd
0.40 Vdd
Min.
2.97
0.0
2.4
2.0
6.0
3.5
–
–
L
= 15 pF (unless otherwise noted)
0.50 Vdd
Divider Ratio (DR)
Typ.
Vdd
3.3
0.0
7.5
4.5
–
–
–
–
256
512
IN
0.60 Vdd
0.15 Vdd
Table
Max.
is the Input Frequency,
3.63
Vdd
0.4
1.2
9.0
6.0
–
–
3.
CY25819
Page 3 of 8
Unit
pF
pF
V
V
V
V
V
V
V
V
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