CS8420-CSZR Cirrus Logic Inc, CS8420-CSZR Datasheet - Page 34
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CS8420-CSZR
Manufacturer Part Number
CS8420-CSZR
Description
IC,Digital Audio Sample Rate Converter,SOP,28PIN
Manufacturer
Cirrus Logic Inc
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34
10.2
SWCLK
VSET
MUTESAO
MUTEAES
DITH
INT[1:0]
TCBLD
SWCLK
7
Miscellaneous Control 1 (01h)
VSET
Causes OMCK to be output through the RMCK pin when the PLL is unlocked
0 - RMCK is driven by the PLL VCO (default)
1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driv-
en by the PLL is driven by OMCK.
Transmitted V bit level
0 - Transmit a 0 for the V bit, indicating that the data is valid, and is normally linear PCM audio
(default)
1 - Transmit a 1 for the V bit, indicating that the data is invalid or is not linear PCM audio data
Mute control for the serial audio output port
0 - Normal output (default)
1 - Mute the serial audio output port
Mute control for the AES3 transmitter output
0 - Normal output (default)
1 - Mute the AES3 transmitter output
Dither Control
0 - Triangular PDF dither applied to output data. The level of the dither is automatically adjusted
to be appropriate for the output word length selected by the SORES bits (default)
1 - No dither applied to output data.
00 - Active high, high output indicates an interrupt condition has occurred (default)
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin.
11 - Reserved
Transmit Channel Status Block pin (TCBL) direction specifier
0 - TCBL is an input (default)
1 - TCBL is an output
Interrupt (INT) output pin control
6
MUTESAO
5
MUTEAES
4
DITH
3
INT1
2
INT0
1
CS8420
TCBLD
DS245F4
0
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