CS8406-DSZR Cirrus Logic Inc, CS8406-DSZR Datasheet - Page 30

• Manufacturer Part Number: CS8406-DSZR
• Description: IC,Digital Audio Transmitter,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

30
SFMT0
SFMT1
APMS
HWCK0
HWCK1
TCBLD
TCBL
CEN
V
U
COPY/C
EMPH
AUDIO
ORIG
TEST
10
20
27
15
16
17
18
19
28
11
4
5
1
3
2
7
8
Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See
page
Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial
audio input port as a master or connected to GND to set the port as a slave.
OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to
VL or pull-down to GND is required to set the appropriate mode. See
Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL to set TCBL as an output.
Connect TCBLD to GND to set TCBL as an input.
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, Hard-
ware Mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, Hardware Mode B is selected, where the COPY/C pin is used
to enter serial channel status data.
Validity Bit (Input) - In Hardware Modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
User Data Bit (Input) - In Hardware Modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
COPY Channel Status Bit/C Bit (Input) - In Hardware Mode A (CEN = 0), the COPY/C and ORIG pins
determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,
see
which is sampled on both edges of LRCK.
Pre-Emphasis Indicator (Input) - In Hardware Mode A (CEN = 0), the EMPH pin low sets the 3 empha-
sis channel status bits to indicate 50/15 µs pre-emphasis of the transmitted audio data. If EMPH is high,
then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
Audio Channel Status Bit (Input) - In Hardware Mode A (CEN = 0), the AUDIO pin determines the
state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
ORIG Channel Status Bit Control (Input) - In Hardware Mode A (CEN = 0), the ORIG and COPY/C
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see
Test Pins (Input) - These pins are unused inputs. It is recommended that these pins be tied to a supply
(VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left float-
ing, however current consumption from VL will increase by 25 µA per TEST pin that is left floating.
Table 2 on page
28.
Table 2 on page
28. In Hardware Mode B, the COPY/C pin becomes the direct C bit input data pin,
28.
Table 4 on page
28.
Table 3 on
CS8406
DS580F4