CS5531-ASZR Cirrus Logic Inc, CS5531-ASZR Datasheet

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... VA- http://www.cirrus.com Ultra-low-noise PGIA with General Description The CS5531/32/33/34 are highly integrated ∆Σ Analog- to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, applications ...

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... TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................4 ANALOG CHARACTERISTICS..........................................................................4 TYPICAL RMS NOISE (NV), CS5531/32/33/34 .................................................7 TYPICAL NOISE-FREE RESOLUTION(BITS), CS5532/34 ............................... DIGITAL CHARACTERISTICS .................................................................... DIGITAL CHARACTERISTICS ....................................................................8 DYNAMIC CHARACTERISTICS ........................................................................9 ABSOLUTE MAXIMUM RATINGS .....................................................................9 SWITCHING CHARACTERISTICS ..................................................................10 2. GENERAL DESCRIPTION .......................................................................................12 2.1. Analog Input ....................................................................................................12 2.1.1. Analog Input Span .................................................................................... 13 2.1.2. Multiplexed Settling Limitations ............................................................13 2.1.3. Voltage Noise Density Performance .....................................................13 2 ...

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... Figure 25. Bridge with Series Resistors .................................................................................. 42 LIST OF TABLES Table 1. Conversion Timing – Single Mode ............................................................................ 34 Table 2. Conversion Timing – Continuous Mode .................................................................... 34 Table 3. Command Byte Pointer ............................................................................................. 35 Table 4. Output Coding for 16-bit CS5531 and CS5533......................................................... 36 Table 5. Output Coding for 24-bit CS5532 and CS5534......................................................... 37 DS289F5 CS5531/32/33/34-AS 3 ...

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... Unipolar Full-scale Error Full-scale Drift Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C. 2. Specifications guaranteed by design, characterization, and/or test. LSB is 16 bits for the CS5531/33 and LSB is 24 bits for the CS5532/34. 3. This specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. Drift over specified temperature range after calibration at power- ° ...

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... VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions. DS289F5 (Continued) Gain = 1 Gain = 16, 32, 64 (Note 5) Gain = 1 (Note 6, 7) Gain = 16, 32, 64 Gain = 1 Gain = 16, 32, 64 dc, Gain = 1 dc, Gain = 64 50 (VREF+) - (VREF-) (Note 50 Bipolar/Unipolar Mode Bipolar Mode Unipolar Mode CS5531/32/33/34-AS Min Typ Max Unit VA- - VA+ VA- + 0.7 - VA 1200 - - 200 - pA/√Hz - ...

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... All outputs unloaded. All input CMOS levels. 9. Power is specified when the instrumentation amplifier (Gain ≥ on. Analog supply current is reduced by approximately 1/2 when the instrumentation amplifier is off (Gain = 1). 10. Tested with 100 mV change on VA+ or VA-. 6 (Continued) Parameter (Notes 8 and 9) CS5531/32/33/34-AS Max Min Typ - ...

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... TYPICAL RMS NOISE (nV), CS5531/32/33/34 (See notes 11, 12 and 13) Output Word -3 dB Filter Rate (Sps) Frequency (Hz) 7.5 1.94 15 3.88 30 7.75 60 15.5 120 31 240 62 480 122 960 230 1,920 390 3,840 780 Notes: 11. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C. ...

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... Symbol All Pins Except SCLK V IH SCLK All Pins Except SCLK V IL SCLK = -1 out OH SDO -5.0 mA out = 1 out OL SDO 5.0 mA out out CS5531/32/33/34-AS Min Typ Max 0.6 VD+ - VD+ (VD+) - 0.45 - VD+ 0.0 - 0.8 0.0 0.6 (VA (VD (VA-) + 0.4 0.4 - ±1 ± ±10 - ...

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... Positive Digital VD+ Positive Analog VA+ Negative Analog VA- (Notes 23 and 24 OUT (Note 25) PDN VREF pins V INR AIN Pins V INA V IND T T stg CS5531/32/33/34-AS Ratio f MCLK/ 1/OWR 5/OWR + 3/OWR s sinc5 t 5/OWR s refers to the 3200 Sps (FRS = 1) or 3840 Sps Min Typ Max -0.3 - +6.0 -0 ...

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... MCLK (Note 27) t rise SCLK Any Digital Output (Note 27) t fall SCLK Any Digital Output (Note 28) t ost SCLK Pulse Width High t 1 Pulse Width Low CS5531/32/33/34-AS Min Typ Max Unit 1 4.9152 5 MHz 1.0 µ 100 µ 1.0 µ 100 µ ...

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... DS289F5 Figure 1. SDI Write Timing (Not to Scale Figure 2. SDO Read Timing (Not to Scale) CS5531/32/33/34- ...

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... Schmitt-trigger input on the serial clock (SCLK). 2.1. Analog Input Figure 3 illustrates a block diagram of the CS5531/32/33/34. The front end consists of a multi- plexer, a unity gain coarse/fine charge input buffer, and a programmable gain chopper-stabilized instru- mentation amplifier. The unity gain buffer is activat- ...

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... Gain = 1.0 and Offset = 0.0). 2.1.2. Multiplexed Settling Limitations The settling performance of the CS5531/32/33/34 in multiplexed applications is affected by the sin- gle-pole, low-pass filter which follows the instru- mentation amplifier (see Figure 3). To achieve data sheet settling and linearity specifications rec- ommended that C0G capacitor be used ...

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... DAC if desired. 2.2. Overview of ADC Register Structure and Operating Modes The CS5531/32/33/34 ADCs have an on-chip con- troller, which includes a number of user-accessible registers. The registers are used to hold offset and gain calibration results, configure the chip's operat- ing modes, hold conversion instructions, and to store conversion data words ...

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... System Initialization The CS5531/32/33/34 provide no power-on-reset function. To initialize the ADCs, the user must per- form a software reset by resetting the ADC’s serial port with the Serial Port Initialization sequence. ...

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... The RV bit in the Configuration Register is set to indicate a valid reset has occurred. The RS bit should be written back to logic “0” to complete the 16 CS5531/32/33/34-AS reset cycle. After a system initialization or reset, the on-chip controller is initialized into command mode where it waits for a valid command (the first 8-bits written into the serial port are shifted into the command register) ...

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... These bits are used as pointers to the Channel-Setup registers. Either a single con- version or continuous conversions are performed on the channel setup register pointed to by these bits. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved CS5531/32/33/34- RSB2 RSB1 RSB0 CC2 ...

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... These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[1:0] (Channel Select Bits) 00 Offset Register 1 (All devices) 01 Offset Register 2 (All devices) 10 Offset Register 3 (CS5533/34 only) 11 Offset Register 4 (CS5533/34 only CS1 CS0 R/W CS5531/32/33/34- DS289F5 ...

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... Channel-Setup Register 2 (All devices) 10 Channel-Setup Register 3 (All devices) 11 Channel-Setup Register 4 (All devices) READ/WRITE CONFIGURATION REGISTER D7(MSB Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. DS289F5 CS1 CS0 R CS1 CS0 R R/W CS5531/32/33/34- ...

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... CSRP [2:0] (Channel Setup Register Pointer Bits) 000 Setup 1 (All devices) 001 Setup 2 (All devices) 010 Setup 3 (All devices) 011 Setup 4 (All devices) 100 Setup 5 (All devices) 101 Setup 6 (All devices) 110 Setup 7 (All devices) 111 Setup 8 (All devices CSRP1 CSRP0 CS5531/32/33/34- DS289F5 ...

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... Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. DS289F5 CSRP1 CSRP0 CS5531/32/33/34- CC2 CC1 CC0 ...

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... Serial Port Interface The CS5531/32/33/34’s serial interface consists of four control lines: CS, SDI, SDO, SCLK. Figure 7 details the command and data word timing. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied low, the port can function as a three-wire interface. ...

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... In the CS5531/32, there are two gain and offset registers, and in the CS5533/34, there are four gain and offset registers. There are four chan- nel setup registers in all parts ...

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... VRS setting. As the models show, the reference includes a coarse/fine charge 24 CS5531/32/33/34-AS buffer which reduces the dynamic current demand of the external reference. The reference’s input buffer is designed to accom- modate rail-to-rail (common-mode plus signal) in- put voltages ...

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... Sps when using a 4.9152 MHz clock. When using other clock frequencies, these selectable word rates will scale linearly with the clock frequency that is used. CS5531/32/33/34-AS φ Fine 1 φ Coarse 2 ...

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... Calibration registers used are based on the CS1-CS0 bits of the referenced Setup. 1 Calibration registers used are based on the OG1-OG0 bits of the referenced Setup. 26 D26 D25 D24 D23 IS GB VRS A1 A0 D10 CS5531/32/33/34-AS D22 D21 D20 D19 D18 OLS NU OGS FRS D17 D16 ...

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... Channel Setup Registers. Each 32-bit CSR is individually accessible and contains two 16-bit Setups example, to con- figure Setup 1 in the CS5531/32/33/34 with the write individual channel-setup register command (0x05 hexadecimal), bits CSR 1 con- tains the information for Setup 1 and bits contain the information for Setup 2 ...

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... U/B D10 WR3 WR2 WR1 WR0 U/B WR (FRS = 1) 100 Sps 50 Sps 25 Sps 12.5 Sps 6.25 Sps 3200 Sps 1600 Sps 800 Sps 400 Sps 200 Sps CS5531/32/33/34-AS D21 D20 D19 D18 D17 OL1 OL0 DT OCD OG1 OL1 OL0 DT OCD OG1 DS289F5 ...

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... CS0 bits of the Setup) will be used. 00 Use offset and gain register from physical channel 1 01 Use offset and gain register from physical channel 2 10 Use offset and gain register from physical channel 3 11 Use offset and gain register from physical channel 4 DS289F5 CS5531/32/33/34-AS 29 ...

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... Calibration Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5531/32/33/34 offer both self-calibration and system calibration. Note: After the ADCs are reset, they are functional and can perform measurements without being calibrated (remember that the VRS bit in the configuration register must be properly configured) ...

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... Only one calibration is performed with each command byte. To calibrate all the channels, additional calibration commands are necessary. 2.5.5. Self-calibration The CS5531/32/33/34 offer both self-offset and self-gain calibrations. For the self-calibration of offset, the converters internally tie the inputs of the 1x amplifier together and routes them to the AIN- pin as shown in Figure 11 ...

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... AIN Figure 13. System Calibration of Offset 32 CS5531/32/33/34-AS channels that are used at these rates should also be calibrated in one of these word rates, and channels used in the lower word rates (120 Sps and lower) should be calibrated at one of these lower rates. Since higher word rates result in conversion words ...

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... Setup (see Section 2.3.7 for more details). If factory calibration of the user’s system is per- formed using the system calibration capabilities of the CS5531/32/33/34, the offset and gain register contents can be read by the system microcontroller and recorded in non-volatile memory. These same calibration words can then be uploaded into the off- ...

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... OWRs less than 3200 Sps, MCLK = 4.9152 MHz) or first five (for OWR ≥ 3200 Sps) conversions in continuous conversion mode, as residual filter coefficients must be flushed from the filter before accurate conversions are performed. CS5531/32/33/34-AS 8 (FRS = ± ± DS289F5 ...

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... Register is set to ‘0’. The command issued is 4 ‘10011001’. This instructs the converter to perform 5 a self offset calibration referencing Setup 4 6 (CSRP2 - CSRP0 = ‘011’). In this example, Setup 7 4 points to physical channel 2. After the command 8 is received and decoded, the ADC performs a self CS5531/32/33/34-AS 35 ...

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... CS OSC2 Figure 15. Synchronizing Multiple ADCs 2.8. Conversion Output Coding The CS5531/33 output 16-bit data conversion words and the CS5532/34 output 24-bit data con- version words. To read a conversion word the user must read the conversion data register. The conver- sion data register is 32 bits long and outputs the conversions MSB first ...

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... Conversion Data Bits [31:16 for CS5531/33; 31:8 for CS5532/34] These bits depict the latest output conversion. NU (Not Used) [15:3 for CS5531/33; 7:3 for CS5532/34] These bits are masked logic zero. OF (Over-range Flag Bit) [2] 0 Bit is clear when over-range condition has not occurred. ...

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... Digital Filter The CS5531/32/33/34 have linear phase digital fil- ters which are programmed to achieve a range of output word rates (OWRs) as stated in the Channel- Setup Register Descriptions section. The ADCs use 5 a Sinc digital filter to output word rates at 3200 Sps and 3840 Sps (MCLK = 4.9152 MHz). Other ...

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... In this scheme, OSC1 should be left uncon- nected. OSC1 DS289F5 2.11. Power Supply Arrangements The CS5531/32/33/34 are designed to operate from single or dual analog supplies and a single digital supply. The following power supply connections are possible: VA+ = +5V; VA- = 0V; VD+ = +3V to +5V VA+ = +2.5V; VA- = -2.5V; VD+ = +3V to +5V VA+ = +3V ...

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... V Analog Supply - Figure 21. CS5532 Configured with a Single +5 V Supply 40 10 Ω 0.1 µ VA+ VD+ OSC2 18 VREF+ 17 VREF- 3 OSC1 CS5532 AIN1+ 2 AIN1- SDI 20 AIN2+ SDO 19 AIN2- SCLK DGND 6 16 CS5531/32/33/34-AS 0.1 µF Optional 9 Clock Source 4.9152 MHz Serial Data 12 Interface 11 DS289F5 ...

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... VA+ VD+ 18 OSC2 VREF+ 17 VREF- 3 OSC1 CS5532 AIN1+ 2 AIN1- SDI 20 AIN2+ SDO 19 AIN2- SCLK DGND 6 16 CS5531/32/33/34- Digital 0.1 µF Supply Optional 9 Clock Source 4.9152 MHz Serial Data 12 Interface 11 0.1 µF Optional 9 Clock Source 4.9152 MHz Serial Data 12 Interface 11 41 ...

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... Figure 24. CS5532 Configured for Thermocouple Measurement V+ ( Ω 0.1 µF 5 VA+ VD+ 1 AIN1+ OSC2 2 AIN1 CS5532 VREF+ 17 VREF- 20 AIN2+ Cold 19 AIN2- Junction DGND Figure 25. Bridge with Series Resistors CS5531/32/33/34-AS 0.1 µF 15 Optional 9 Clock Source 4.9152 MHz 10 OSC1 Serial SDI Data 12 SDO Interface 11 SCLK (b) DS289F5 ...

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... To accommodate for this recommended that a software delay of approximately 20 ms start the processor’s ADC initialization code. Next, since the CS5531/32/33/34 do not provide a power- on-reset function, the user must first initialize the ADC to a known state. This is accomplished by re- setting the ADC’s serial port with the Serial Port Initialization sequence ...

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... DIFFERENTIAL ANALOG INPUT VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT 6 19 VA+ DGND DIGITAL GROUND 7 18 VA- VD+ POSITIVE DIGITAL POWER CHIP SELECT SDI SERIAL DATA INPUT 10 15 SDO SERIAL DATA OUT OSC2 11 14 OSC1 SERIAL CLOCK INPUT 12 13 SCLK CS5531/32/33/34-AS DS289F5 ...

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... C1 Amplifier Capacitor Inputs. Connections for the instrumentation amplifier’s capacitor. Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. VD+ - Positive Digital Power. Positive digital supply voltage (nominally +3 V). VA- - Negative Analog Power. Negative analog supply voltage. DGND - Digital Ground. Digital Ground. DS289F5 CS5531/32/33/34-AS 45 ...

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... When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. 46 CS5531/32/33/34-AS DS289F5 ...

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... CS5531/32/33/34-AS Package 20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP, Lead Free 24-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP, Lead Free 20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP, Lead Free 24-pin 0.2" ...

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... CS5531/32/33/34- ∝ END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 7.50 1 8.20 5.60 1 0.69 1.03 0° ...

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... CS5531/32/33/34- ∝ END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 8.50 1 8.20 5.60 1 0.69 1.03 0° ...

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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 50 CHANGES www.cirrus.com CS5531/32/33/34-AS DS289F5 ...