CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 32

• Manufacturer Part Number: CS5368-DQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

DS624A1
5.5
5.6
5.7
5.8
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
03h (OVFM) Overflow Mask Register
The Overflow Mask Register is used to allow or prevent individual channel overflow events from
creating activity on the OVFL pin. When a particular bit is set low in the Mask register, the
corresponding overflow bit in the Overflow Status register is prevented from causing any activity
on the OVFL pin.
04h (HPF) High-Pass Filter Register
05h Reserved
06h (PDN) Power Down Register
Default:
Default:
The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each
channel. These filters are used to perform DC offset calibration, a procedure that is detailed in
“DC Offset Control” on page 26
Default:
The Power Down Register is used as needed to reduce the chip’s power consumption.
Bit[7] RESERVED
Bit[6] RESERVED
Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.
Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscil-
lator core is shut down, and no clock is supplied to the chip. If the chip is running off an externally
supplied clock at the MCLK pin, it is also prevented from clocking the device internally.
Bit[3:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial
data outputs are forced to all zeroes.
OVFM8
HPF8
7
7
7
7
-
RESERVED
0xFF, all overflow interrupts enabled.
0x00, all high-pass filters enabled.
0x00 - everything powered up
OVFM7
HPF7
6
6
6
6
-
PDN-BG
.
OVFM6
HPF6
5
5
5
5
-
PDN-OSC
OVFM5
HPF5
4
4
4
4
-
OVFM4
PDN87
HPF4
3
3
3
3
-
OVFM3
PDN65
HPF3
2
2
2
2
-
OVFM2
PDN43
HPF2
1
1
1
1
-
CS5368
OVFM1
PDN21
HPF1
0
0
0
0
-
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