CS48540-DQZR Cirrus Logic Inc, CS48540-DQZR Datasheet - Page 9

• Manufacturer Part Number: CS48540-DQZR
• Description: IC,DSP,32-BIT,QFP,48PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Fixed Pointr

Specifications of CS48540-DQZR

• Interface: I²C, SPI
• Clock Rate: 150MHz
• On-chip Ram: 96kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1284 - KIT USB EVALUATION FOR CDB48500
• Non-volatile Memory: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2.5 PLL-based Clock Generator
4.2.6 Hardware Watchdog Timer
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
4.3.2 Termination Requirements
4.3.3 Pads
4.4 Application Code Security
DS734F3
to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock
domain can be output on the DAO port for driving audio converters. The CS485xx defaults to running
from the external reference frequency and is switched to use the PLL output after overlays have
been loaded and configured, either through master boot from an external FLASH or through host
control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output
frequency ratio is selectable between 1:1 (default) or 2:1.
watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This
peripheral ensures that the CS485xx will reset itself in the event of a temporary system failure. In
stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode
(that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and
the DSP should be rebooted and re-configured.
the CS485xx Hardware User’s Manual.
CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up
resistor is required for proper operation.
reset. A detailed explanation of termination requirements for each communication mode select pin
can be found in the CS485xx Hardware User’s Manual.
it may contain. A secret, customer-specific key is used to encrypt the program code that is to be
stored external to the device. Please contact your local Cirrus representative for details.
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used
The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The
Many of the CS485xx family pins are multi-functional. For details on pin functionality please refer to
Open-drain pins on the CS485xx must be pulled high for proper operation. Please refer to the
Mode select pins in the CS485xx family are used to select the boot mode upon the rising edge from
The CS485xx I/Os operate from the 3.3 V supply and are 5 V tolerant.
The external program code may be encrypted by the programmer to protect any intellectual property
Copyright 2009 Cirrus Logic, Inc.
CONFIDENTIAL
32-bit Audio Decoder DSP Family
CS485xx Family Data Sheet
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