CS43L22-CNZR Cirrus Logic Inc, CS43L22-CNZR Datasheet - Page 40

• Manufacturer Part Number: CS43L22-CNZR
• Description: IC Low Power DAC W/ClassD Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L22-CNZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1529 - BOARD EVAL FOR CS43L22
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

40
7.4.6
7.5
7.5.1
7.5.2
7.5.3
7.5.4
M/S
7
Interface Control 1 (Address 06h)
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
Note:
Master/Slave Mode
Configures the serial port I/O clocking.
SCLK Polarity
Configures the polarity of the SCLK signal.
DSP Mode
Configures a data-packed interface format for the DAC.
Notes:
1. Select the audio word length using the AWL[1:0] bits
2. The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.
DAC Interface Format
Configures the digital interface format for data on SDIN.
Note:
page
MCLKDIV2
0
1
Application:
M/S
0
1
INV_SCLK
0
1
DSP
0
1
Application:
DACDIF[1:0]
00
01
10
11
Application:
41).
INV_SCLK
In Slave Mode, this bit is ignored when the AUTO bit
Select the audio word length for Right Justified using the AWL[1:0] bits
6
MCLK signal into DAC
No divide
Divided by 2
“Serial Port Clocking” on page 29
Serial Port Clocks
Slave (input ONLY)
Master (output ONLY)
SCLK Polarity
Not Inverted
Inverted
DSP Mode
Disabled
Enabled
“DSP Mode” on page 31
DAC Interface Format
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified
Reserved
“Digital Interface Formats” on page 30
Reserved
5
Confidential Draft
DSP
4
3/4/10
DACDIF1
3
(“Audio Word Length” on page
(“Auto-Detect” on page
DACDIF0
2
(“Audio Word Length” on
AWL1
1
38) is disabled.
41).
CS43L22
AWL0
DS792F2
0