CS4352-DZZ Cirrus Logic Inc, CS4352-DZZ Datasheet - Page 13

• Manufacturer Part Number: CS4352-DZZ
• Description: IC,D/A CONVERTER,DUAL,24-BIT,TSSOP,20PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS4352-DZZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 158mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1518 - BOARD EVAL FOR CS4352 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS684F2
4.4
4.5
4.6
4.6.1
De-Emphasis Control
The device includes on-chip digital de-emphasis.
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in sample rate, Fs. The
De-emphasis error will increase for sample rates other than 44.1 kHz
When pulled to VL, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM
pin turns off the de-emphasis filter.
Note:
Recommended Power-Up Sequence
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the power-up
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized.
rangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS4352 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted
coupling into the DAC.
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-
pacitor should still be placed on each supply pin.
Note:
The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements.
clocks are locked to the appropriate frequencies, as discussed in
main low and VBIAS will be connected to VA.
sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
De-emphasis is only available in Single-Speed Mode.
All decoupling capacitors should be referenced to analog ground.
-10dB
Gain
0dB
dB
Figure 6. De-Emphasis Curve
3.183 kHz
T1=50 µs
F1
Figure 6
10.61 kHz
F2
shows the de-emphasis curve for Fs equal to
Figure 2
T2 = 15 µs
Frequency
shows the recommended power ar-
Section
4.2. In this state, VQ will re-
CS4352
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