CS4351-DZZR Cirrus Logic Inc, CS4351-DZZR Datasheet - Page 15

• Manufacturer Part Number: CS4351-DZZR
• Description: IC,D/A CONVERTER,DUAL,24-BIT,TSSOP,20PIN
• Manufacturer: Cirrus Logic Inc

DS566F1
4. APPLICATIONS
4.1
4.1.1
4.1.2
4.2
Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will
depend on whether the Auto-Detect Defeat bit is enabled/disabled.
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (F
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard au-
dio sample rates and the required MCLK frequency, are illustrated in
Refer to
to the
frequencies.
Auto-Detect Enabled
The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct mode
when the input sample rate (F
in
Auto-Detect Disabled
The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In this
state, the CS4351 will not auto-detect the correct mode based on the input sample rate (F
tional mode must then be set manually according to one of the ranges illustrated in
to
not supported. In stand-alone mode it is not possible to disable auto-detect of sample rates.
Table
Section 6.2.3
“Switching Specifications - Serial Audio Interface” section on page 10
FM1
0
0
1
1
Section 4.3
1. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (F
170 kHz - 200 kHz
84 kHz - 100 kHz
for implementation details. Sample rates outside the specified range for each mode are
4 kHz - 50 kHz
for the required SCLK timing associated with the selected Digital Interface Format and
FM0
0
1
0
1
s
), defined by the LRCK frequency, falls within one of the ranges illustrated
Input Sample Rate (F
Table 2. CS4351 Mode Select
Table 1. CS4351 Auto-Detect
S
Auto speed mode detect
)
100 kHz - 200 kHz
50 kHz - 100 kHz
4 kHz - 50 kHz
S
)
s
), must be synchronously derived from the
Double-Speed Mode
Single-Speed Mode
Quad-Speed Mode
Tables 3
MODE
Double-Speed Mode
Single-Speed Mode
Quad-Speed Mode
for the maximum allowed clock
MODE
Auto
through 5.
Table
2. Please refer
s
). The opera-
CS4351
15