CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 52

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

CS42L51
6.6
ADC Control (Address 06h)
7
6
5
4
3
2
1
0
ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ
SOFTB
ZCROSSB
SOFTA
ZCROSSA
ADCX High-Pass Filter Enable (ADCX_HPFEN)
Default: 1
0 - High-pass filter is disabled
1 - High-pass filter is enabled
Function:
When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter
will be disabled. For DC measurements, this bit must be cleared to ‘0’. See “ADC Digital Filter Characteris-
tics” on page 15.
ADCX High-Pass Filter Freeze (ADCX_HPFRZ)
Default: 0
0 - Continuous DC Subtraction
1 - Frozen DC Subtraction
Function:
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC mea-
surements, this bit must be set to ‘1’. See “ADC Digital Filter Characteristics” on page 15.
Soft Ramp CHX Control (SOFTX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital atten-
uation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period.
PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB
steps and be implemented on a signal zero crossing.
Zero Cross CHX Control (ZCROSSX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible
artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximate-
ly 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function
is independently monitored and implemented for each channel.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps
and be implemented on a signal zero crossing.
The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.
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