CS4299-JQZR Cirrus Logic Inc, CS4299-JQZR Datasheet - Page 28

• Manufacturer Part Number: CS4299-JQZR
• Description: IC AC97 Codec With SRC
• Manufacturer: Cirrus Logic Inc
• Series: SoundFusion™r
• Type: Audio Codec '97r

Specifications of CS4299-JQZR

• Data Interface: Serial
• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 87
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• No. Of Dacs: 1
• No. Of Input Channels: 6
• No. Of Output Channels: 2
• Adc / Dac Resolution: 20bit
• Adcs / Dacs Signal To Noise Ratio: 70dB
• Sampling Rate: 48kSPS
• Supply Voltage Range: 3.135V To 3.465V, 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14
ID[1:0]
AMAP
VRA
Default
4.15
VRA
Default
28
28
D15
D15
ID1
0
Extended Audio ID Register (Index 28h)
Extended Audio Status/Control Register (Index 2Ah)
D14
D14
ID0
0
D13
D13
0
0
Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When
ID[1:0] = 01, 10, or 11, the CS4297A is a secondary audio codec. The state of the ID[1:0] bits
is determined at power-up from the ID[1:0]# pins.
Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link
slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode
Control Register (Index 5Eh). The PCM playback and capture slots are mapped according to
Table 8 on page 30.
Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is supported.
This bit always returns ‘1’, indicating that variable rate PCM audio is available.
x201h. Where x is determined by the state of ID[1:0]# input pins. The Extended Audio ID Reg-
ister (Index 28h) is a read only register.
Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC Rate
Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). The bit must be ‘set’ in
order to use variable PCM playback or capture rates. The VRA bit also serves as a powerdown
for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC Rate Register
(Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC
data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at
‘0’.
0000h
D12
D12
0
0
D11
D11
0
0
D10
D10
0
0
AMAP
D9
D9
0
D8
D8
0
0
D7
D7
0
0
D6
D6
0
0
D5
D5
0
0
D4
D4
0
0
D3
D3
0
0
D2
D2
0
0
CS4299
D1
D1
CS4299
0
0
DS319PP6
VRA
VRA
D0
D0