CS4272-CZZR Cirrus Logic Inc, CS4272-CZZR Datasheet - Page 34
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CS4272-CZZR
Manufacturer Part Number
CS4272-CZZR
Description
IC,Soundcard Circuits,TSSOP,28PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS4272-CZZR.pdf
(53 pages)
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5.5
The Mute Control pins become active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is in-
correct, and during power-down. The Auto-Mute function causes the MUTEC pin corresponding to an individual
channel to activate following the reception of 8192 consecutive audio samples of static 0 or -1 on the respective
channel. A single sample of non-zero data on this channel will cause the MUTEC pin to deactivate. In Control Port
Mode, however, auto-mute detection and muting can become dependent on either channel if the MuteB=A function
is enabled. The MUTEC pins are intended to be used as control for an external mute circuit in order to add off-chip
mute capability.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in
extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pins are active-
low. See Figure 16 below for a suggested active-low mute circuit.
5.6
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the MCLK and LRCK must be the same for all of the CS4272’s in the system. If only one
MCLK source is needed, one solution is to place one CS4272 in Master Mode, and slave all of the other CS4272’s
to the one master. If multiple MCLK sources are needed, a possible solution would be to supply all clocks from the
same external source and time the CS4272 reset with the inactive edge of MCLK. This will ensure that all converters
begin sampling on the same clock edge.
5.7
As with any high resolution converter, the CS4272 requires careful attention to power supply and grounding arrange-
ments if its potential performance is to be realized. Figure 8 shows the recommended power arrangements, with VA
and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply
(VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be
powered from VD. Power supply decoupling capacitors should be as near to the CS4272 as possible, with the low
value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the VREF and
VCOM pins in order to avoid unwanted coupling into the modulators. The VREF and VCOM decoupling capacitors,
particularly the 0.1 µF, must be positioned to minimize the electrical path from VREF and AGND. The CDB4272
evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, con-
nect the CS4272 digital outputs only to CMOS inputs.
34
Mute Control
Synchronization of Multiple Devices
Grounding and Power Supply Decoupling
CS4272
MUTEC
AOUT
Figure 16. Suggested Active-Low Mute Circuit
LPF
+V
-V
EE
EE
Couple
MMUN2111LT1
AC
+V
A
-V
EE
10 kΩ
560 Ω
2 kΩ
47 kΩ
Audio
Out
CS4272
DS593F1