CS42448-CQZR Cirrus Logic Inc, CS42448-CQZR Datasheet - Page 37

• Manufacturer Part Number: CS42448-CQZR
• Description: IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

DS648F2
4.8
4.9
SCL
SDA
Interrupts
The 42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be configured as an active low or active high CMOS
driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple pe-
ripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See
(Address 19h) (Read Only)” on page
dition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of
level sensitive or edge sensitive modes within the microcontroller, many different configurations are possi-
ble, depending on the needs of the system designer.
Recommended Power-Up Sequence
1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10010xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
START
default settings and VQ will remain low.
Figure
0
1
CHIP ADDRESS (WRITE)
1
0
25, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
2
1
3
0 AD1 AD0 0
4
5
6
7
ACK
8
Figure 25. Control Port Timing, I²C Read
INCR
9
10 11
6
5
MAP BYTE
12 13 14 15
4
51. Each source may be masked off through mask register bits. In ad-
3
2
1
16
0
ACK
STOP
17 18
START
19
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
0
1
0 AD1 AD0 1
25
26 27 28
ACK
7
DATA
0
ACK
DATA +1
7
0
DATA + n
7
0
ACK
CS42448
NO
STOP
“Status
37