CS42435-DMZR Cirrus Logic Inc, CS42435-DMZR Datasheet - Page 46

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CS42435-DMZR

Manufacturer Part Number
CS42435-DMZR
Description
IC,Soundcard Circuits,CMOS,QFP,52PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42435-DMZR

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
4 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
105 / 108 (Differential), 102 / 105 (Single-Ended)
Voltage - Supply, Analog
3.14 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
52-MQFP, 52-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42435-DMZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
46
7.12
7.12.1 Invert Signal Polarity (INV_AINX)
7.13
7.13.1 Clock Error (CLK ERROR)
7.13.2 ADC Overflow (ADCX_OVFL)
Reserved
Reserved
7
7
ADC Channel Invert (Address 17h)
Status (Address 19h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active
during the error condition. See
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42435 ADC signal path of each of the
associated ADC’s.
Reserved
Reserved
6
6
Reserved
Reserved
5
5
Table 7. Example AIN Volume Settings
Binary Code
0000 0000
1000 0000
0011 0000
0111 1111
1111 1110
1111 1111
“System Clocking” on page 31
Reserved
···
···
···
Reserved
4
4
CLK Error
Volume Setting
INV_A4
3
3
-0.5 dB
+24 dB
+24 dB
-64 dB
-1 dB
0 dB
···
···
···
for valid clock ratios.
Reserved
INV_A3
2
2
ADC2_OVFL
INV_A2
1
1
CS42435
ADC1_OVFL
INV_A1
DS685F3
0
0

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