CS42325-CQZR Cirrus Logic Inc, CS42325-CQZR Datasheet - Page 61

• Manufacturer Part Number: CS42325-CQZR
• Description: IC 10In, 6Out, 2Vrms Audio Codec WHP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS838A2
6.19.7 ADC Positive Overflow Mask (ADC_OVFLPM)
6.19.8 ADC Negative Overflow Mask (ADC_OVFLNM)
6.20
6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL)
6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER)
AMUTEL
DAC2_
7
Interrupt Status (Address 18h) (Read Only)
This register defaults to 00h and is read only. If the INT pin is active, reading this register clears the interrupt
condition.
This bit serves as a mask for the ADC positive overflow interrupt source. If this bit is cleared, the
ADC_OVFLP interrupt is unmasked, meaning that if the ADC_OVFLP conditions are met in the interrupt
status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the
dress 16h)” register on page
meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the
overflow state of the ADC.
This bit serves as a mask for the ADC negative overflow interrupt source. If this bit is cleared, the
ADC_OVFLN interrupt is unmasked, meaning that if the ADC_OVFLN conditions are met in the interrupt
status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the
dress 16h)” register on page
meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the
overflow state of the ADC.
This bit is read only. When set, indicates that DAC2 left channel has had an auto-mute condition since the
last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive sam-
ples of zeroes or ones on the left channel of SDIN2, will cause this bit to be set. This interrupt status bit
is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the
on page 59
This bit is read only. When set, indicates that DAC2 right channel has had an auto-mute condition since
the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive
samples of zeroes or ones on the right channel of SDIN2, will cause this bit to be set. This interrupt status
bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the
on page 59
Bit Settings
AMUTER
DAC2_
0
1
6
and the status of this bit if DAC2_AMUTELM bit is cleared.
and the status of this bit if DAC2_AMUTERM bit is cleared.
AMUTEL
DAC1_
5
59. If the ADC_OVFLNM bit is set, the ADC_OVFLN condition is masked,
59. If the ADC_OVFLPM bit is set, the ADC_OVFLP condition is masked,
Interrupt has not occurred since the last read of this register.
AMUTER
DAC1_
Interrupt has occurred since the last read of this register.
4
CLKERR
Bit in Interrupt Register
SP2_
3
CLKERR
SP1_
2
“Interrupt Mode (Address 16h)”
“Interrupt Mode (Address 16h)”
OVFLP
ADC_
1
“Interrupt Mode (Ad-
“Interrupt Mode (Ad-
CS42325
OVFLN
ADC_
0
61