CS2300P-DZZ Cirrus Logic Inc, CS2300P-DZZ Datasheet - Page 10

• Manufacturer Part Number: CS2300P-DZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-DZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
5. APPLICATIONS
5.1
5.2
5.3
5.3.1
One Time Programmability
The one time programmable (OTP) circuitry in the CS2300-OTP allows for pre-configuration of the device
prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal
and global. The modal parameters are features which, when grouped together, create a modal configuration
set (see
dynamically selected using the M[1:0] mode select pins (see
maining configuration settings which do not change with the mode select pins. The modal and global pa-
rameters can be pre-set at the factory or user programmed using the customer development kit, CDK2000;
Please see
Timing Reference Clock
The internal LC oscillator is used to generate the timing reference clock. A single 0.1 µF cap must be con-
nected between the FILTP and FILTN pins and FILTN must be connected to ground as shown in
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see
on page
block then translates the desired ratio based off of CLK_IN to one based off of the internal LCO. This allows
the low-jitter internal LCO to be used as the clock which the Frequency Synthesizer multiplies while main-
taining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency
range for CLK_IN is found in the
Parameter Type
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to
skipping mode can only be used when the CLK_IN frequency is below
rameter enables this function.
Global
Modal
Figure 14 on page
9). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
20
“Programming Information” on page 25
ms (t
CS
Figure 4. External Component Requirements for LCO
Configuration Set 0
M[1:0] pins = 00
) at a time (see
Ratio 0
Table 1. Modal and Global Configuration
20). Up to four modal configuration sets can be permanently stored and then
“AC Electrical Characteristics” on page
FILTN
“AC Electrical Characteristics” on page 7
Confidential Draft
Configuration settings set once for all modes.
Configuration Set 1
M[1:0] pins = 01
0.1 µF
3/18/09
Ratio 1
FILTP
for more details.
Table
Configuration Set 2
M[1:0] pins = 10
1). The global parameters are the re-
Ratio 2
80
7.
kHz. The ClkSkipEn global pa-
“Hybrid Analog-Digital PLL”
for specifications). CLK_IN
Configuration Set 3
M[1:0] pins = 11
CS2300-OTP
Ratio 3
DS844PP2
Figure
4.