CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 11
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CS2000CP-CZZ
Manufacturer Part Number
CS2000CP-CZZ
Description
IC General Purpose PLL Crystal
Manufacturer
Cirrus Logic Inc
Type
Fractional N Synthesizerr
Specifications of CS2000CP-CZZ
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/No
Frequency - Max
75MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Frequency-max
75MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1748
CS2000CP-CZZ
CS2000CP-CZZ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS2000CP-CZZ
Manufacturer:
CIRRUS
Quantity:
28
Part Number:
CS2000CP-CZZR
Manufacturer:
CIRRUS
Quantity:
20 000
DS761PP1
4. ARCHITECTURE OVERVIEW
4.1
4.2
Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu-
tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies
the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input
clock ratio is the value of N that is applied to the delta-sigma modulator (see
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase
reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fraction-
al-N divided clock with the original timing reference and generates a control signal. The control signal is fil-
tered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The
delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the
reference clock and the VCO output (thus the one’s density of the modulator sets the fractional value). This
allows the design to be optimized for very fast lock times for a wide range of output frequencies without the
need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference
clock should be stable and jitter-free.
Hybrid Analog-Digital Phase Locked Loop
The addition of the Digital PLL and Fractional-N Logic (shown in
Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical an-
alog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges
without the need to change external loop filter components while maintaining impressive jitter reduction per-
formance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the fre-
quency reference and compares that to the desired ratio. The digital logic generates a value of N which is
then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice
that the frequency and phase of the timing reference signal do not affect the output of the PLL since the
digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which
the loop filter bandwidth can be altered. The PLL bandwidth is automatically set to a wide-bandwidth mode
to quickly achieve lock and then reduced for optimal jitter rejection.
Timing Reference
Clock
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer
Comparator
Phase
Fractional-N
Delta-Sigma
Loop Filter
Modulator
Internal
Divider
N
Voltage Controlled
Figure
Oscillator
5) to the Fractional-N Frequency
Figure
4).
PLL Output
CS2000-CP
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