CAT5261YI-50-T2 ON Semiconductor, CAT5261YI-50-T2 Datasheet - Page 9

• Manufacturer Part Number: CAT5261YI-50-T2
• Description: DPP NV, DUAL 256 TAP, SPI
• Manufacturer: ON Semiconductor

Specifications of CAT5261YI-50-T2

• Lead Free Status / Rohs Status: Compliant

Wiper Control and Data Registers
Wiper Control Register (WCR)
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 256 switches
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written by the host via Write
Wiper Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction; it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power−up.
its contents when the CAT5261 is powered−down. Although
the register is automatically loaded with the value in DR0
upon power−up, this may be different from the value present
at power−down.
Data Registers (DR)
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non−volatile
operation and will take a maximum of 5 ms.
NOTE:
Table 13. INSTRUCTION SET
Read Wiper Control
Register
Write Wiper Control
Register
Read Data Register
Write Data Register
XFR Data Register to
Wiper Control
Register
XFR Wiper Control
Register to Data
Register
Global XFR Data
Registers to Wiper
Control Registers
Global XFR Wiper
Control Registers to
Data Register
Increment/Decrement
Wiper Control Register
Read Status (WIP bit)
The CAT5261 contains two 8−bit Wiper Control
The Wiper Control Register is a volatile register that loses
Each potentiometer has four 8−bit non−volatile Data
Instruction
1/0 = data is one or zero
I3
1
1
1
1
1
1
0
1
0
0
I2
0
0
0
1
1
1
0
0
0
1
I1
0
1
1
0
0
1
0
0
1
0
I0
1
0
1
0
1
0
1
0
0
1
Instruction Set
R1
1/0
1/0
1/0
1/0
1/0
1/0
0
0
0
0
1/0
1/0
1/0
1/0
1/0
1/0
R0
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0
0
0
0
WCR1/
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P1
0
0
0
9
settings for the potentiometer, the Data Registers can be used
as standard memory locations for system parameters or user
preference data.
Write in Process
nonvolatile memory when the CS input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
Instructions
instructions are:
If the application does not require storage of multiple
The contents of the Data Registers are saved to
Five of the ten instructions are three bytes in length. These
♦
♦
♦
♦
♦
WCR0/
wiper position of the selected potentiometer in the
WCR
wiper position in the WCR of the selected
potentiometer
selected Data Register
selected Data Register
when set to “1” signifies a write cycle is in progress.
Read Wiper Control Register – read the current
Write Wiper Control Register – change current
Read Data Register – read the contents of the
Write Data Register – write a new value to the
Read Status – Read the status of the WIP bit which
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P0
0
0
1
Read the contents of the Wiper Control Register
pointed to by P1−P0
Write new value to the Wiper Control Register
pointed to by P1−P0
Read the contents of the Data Register pointed
to by P1−P0 and R1−R0
Write new value to the Data Register pointed to
by P1−P0 and R1−R0
Transfer the contents of the Data Register
pointed to by P1−P0 and R1−R0 to its
associated Wiper Control Register
Transfer the contents of the Wiper Control
Register pointed to by P1−P0 to the Data
Register pointed to by R1−R0
Transfer the contents of the Data Registers
pointed to by R1−R0 of all four pots to their
respective Wiper Control Registers
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1−R0 of all four pots
Enable Increment/decrement of the Control
Latch pointed to by P1−P0
Read WIP bit to check internal write cycle status
Operation