CAT5241YI-25-T2 ON Semiconductor, CAT5241YI-25-T2 Datasheet - Page 9
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CAT5241YI-25-T2
Manufacturer Part Number
CAT5241YI-25-T2
Description
DPP NV, QUAD 64 TAPS, I2C
Manufacturer
ON Semiconductor
Datasheet
1.CAT5241YI-25-T2.pdf
(16 pages)
Specifications of CAT5241YI-25-T2
Lead Free Status / Rohs Status
Compliant
Instructions and Register Description
Slave Address Byte
processor is called the Slave/DPP Address Byte. The most
significant four bits of the slave address are a device type
identifier. These bits for the CAT5241 are fixed at 0101[B]
(refer to Figure 8).
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5241 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
or tied to V
The first byte sent to the CAT5241 from the master/
The next four bits, A3 − A0, are the internal slave address
CC
or V
(MSB)
(MSB)
ID3
I3
SS
0
.
Device Type Identifier
ID2
I2
1
Instruction
Opcode
ID1
Figure 8. Identification Byte Format
I1
Figure 9. Instruction Byte Format
0
http://onsemi.com
ID0
I0
1
9
WCR/Pot Selection
Instruction Byte
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The P1 and P0 bits point to one of four Wiper Control
Registers. The least two significant bits, R1 and R0, point to
one of the four data registers of each associated
potentiometer. The format is shown in Figure 9.
Table 11. DATA REGISTER SELECTION
P1
The next byte sent to the CAT5241 contains the
A3
Data Register Selected
P0
A2
Slave Address
DR0
DR1
DR2
DR3
R1
A1
Data Register
Selection
(LSB)
(LSB)
A0
R0
R1
0
0
1
1
R0
0
1
0
1