AM29LV160BT-90EI AMD (ADVANCED MICRO DEVICES), AM29LV160BT-90EI Datasheet - Page 53

• Manufacturer Part Number: AM29LV160BT-90EI
• Description: IC 16MX16, 3V 100K FLSH, TOP B
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

REVISION SUMMARY
Revision F (January 1998)
Distinctive Characteristics
Changed typical read and program/erase current
specifications.
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Figure 2, In-System Sector Protect/Unprotect
Algorithms
Corrected A6 to 0, Changed wait specification to 150
µ
DC Characteristics
Changed typical read and program/erase current
specifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations:
Changed t
options.2w
Erase and Programming Performance
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Physical Dimensions
Corrected dimensions for package length and width in
FBGA illustration (standalone data sheet version).
Revision F+1
Table 9, Command Definitions
Corrected the byte-mode address in the sixth write
cycle of the chip erase command sequence to AAAh.
Revision F+2
Figure 2, In-System Sector Protect/Unprotect
Algorithms
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the path from “Protect another sec-
tor?” back to setting up the next sector address.
DC Characteristics
Changed I
that OE# is at V
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations: Corrected the notes refer-
ence for t
100% tested. Corrected the note reference for t
This parameter is not 100% tested.
Temporary Sector Unprotect Table
s on sector protect and 15 ms on sector unprotect.
WHWH1
CC1
CP
to 35 ns for 70R, 80, and 90 speed
test conditions and Note 1 to indicate
IH
and t
for the listed current.
WHWH2
. These parameters are
VCS
Am29LV160B
.
Added note reference for t
100% tested.
Figure 22, Sector Protect/Unprotect Timing
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million
cycles.
Revision G (January 1999)
Global
Added 70R speed option, changed 80R speed option
to 80.
Distinctive Characteristics
Changed process technology to 0.32 µm.
DC Characteristics
Moved V
to notes.
Connection Diagrams
Corrected the reverse TSOP drawing to show orienta-
tion and pin 1 indicators.
Distinctive Characteristics
Added 20-year data retention bullet.
Connection Diagrams
Updated FBGA figure.
Ordering Information
Changed FBGA package reference to FBC048; ad-
dded FBGA package marking information.
Physical Dimensions
Changed drawing to FBC048.
Revision G+1 (February 1999)
Connection Diagrams
FBGA: Corrected to indicate that diagram shows the
top view, balls facing down.
Command Definitions Table
Corrected the address in the sixth cycle of the chip
erase sequence to AAAh.
Revision H (November 23, 1999)
AC Characteristics—Figure 17. Program Opera-
tions Timing and Figure 18. Chip/Sector Erase
Operations
CC
max test condition for I
VIDR
. This parameter is not
CC
specifications
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