AM29LV160BT-90EC AMD (ADVANCED MICRO DEVICES), AM29LV160BT-90EC Datasheet - Page 31

• Manufacturer Part Number: AM29LV160BT-90EC
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV160BT-90EC

• Memory Configuration: 2M X 8 / 1M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Interface Type: Parallel
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle
was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation
has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
Standard
Mode
Erase
Suspend
Mode
See “DQ5: Exceeded Timing Limits” for more information.
details.
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend-Program
Operation
Table 10. Write Operation Status
(Note 2)
DQ7#
DQ7#
Data
DQ7
0
1
Am29LV160B
No toggle
Toggle
Toggle
Toggle
Data
DQ6
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the sys-
tem can guarantee that the time between additional
sector erase commands will always be less than 50
μs. See also the “Sector Erase Command Sequence”
section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read
DQ3. If DQ3 is “1”, the internally controlled erase cycle
has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device will accept additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted. Table 10 shows the outputs for DQ3.
(Note 1)
DQ5
Data
0
0
0
0
Data
DQ3
N/A
N/A
N/A
1
No toggle
(Note 2)
Toggle
Toggle
Data
DQ2
N/A
RY/BY#
0
0
1
1
0
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