ADXL346ACCZ-RL7 Analog Devices Inc, ADXL346ACCZ-RL7 Datasheet - Page 16

• Manufacturer Part Number: ADXL346ACCZ-RL7
• Description: 3 Axis, Digital Accelerometer Ope
• Manufacturer: Analog Devices Inc

Specifications of ADXL346ACCZ-RL7

• Axis: X, Y, Z
• Acceleration Range: ±2g, 4g, 8g, 16g
• Sensitivity: 256LSB/g, 128LSB/g, 64LSB/g, 32LSB/g
• Voltage - Supply: 1.7 V ~ 2.75 V
• Output Type: Digital
• Bandwidth: 6.25Hz ~ 3.2kHz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 16-LGA
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: ADXL346ACCZ-RL7TR

ADXL346
Table 9. SPI Digital Input/Output
Parameter
Digital Input
Digital Output
Pin Capacitance
1
Table 10. SPI Timing (T
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
SCLK
SCLK
DELAY
QUIET
DIS
CS ,DIS
S
M
SETUP
HOLD
SDO
R
F
Limits are based on characterization results; not production tested.
The CS , SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
Limits are based on characterization results; not production tested.
The timing values are measured corresponding to the input thresholds (V
Output rise and fall times are measured with a capacitive load of 150 pF.
4
4
Low Level Input Voltage (V
High Level Input Voltage (V
Low Level Input Current (I
High Level Input Current (I
Low Level Output Voltage (V
High Level Output Voltage (V
Low Level Output Current (I
High Level Output Current (I
Min
200
5
5
150
0.3 × t
0.3 × t
5
5
A
SCLK
SCLK
= 25°C, V
IL
Limit
IH
IL
)
IH
)
OL
)
OH
OL
)
OH
)
)
)
)
Max
5
10
40
20
20
2, 3
S
= 2.6 V, V
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD I/O
Test Conditions
V
V
I
I
V
V
f
OL
OH
IN
IN
IN
OL
OH
= 1 MHz, V
= 10 mA
= −4 mA
= V
= 0 V
= V
= V
= 1.8 V)
DD I/O
OL, max
OH, min
Description
SPI clock frequency
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
CS falling edge to SCLK falling edge
SCLK rising edge to CS rising edge
CS rising edge to SDO disabled
CS deassertion between SPI communications
SCLK low pulse width (space)
SCLK high pulse width (mark)
SDI valid before SCLK rising edge
SDI valid after SCLK rising edge
SCLK falling edge to SDO/SDIO output transition
SDO/SDIO output low to output high transition
SDO/SDIO output high to output low transition
Rev. A | Page 16 of 40
IL
1
IN
and V
= 2.6 V
IH
) given in Table 9.
Min
0.7 × V
−0.1
0.8 × V
10
DD I/O
DD I/O
Limit
1
Max
0.3 × V
0.1
0.2 × V
−4
8
DD I/O
DD I/O
Unit
V
V
μA
μA
V
V
mA
mA
pF