ADUM5201ARWZ Analog Devices Inc, ADUM5201ARWZ Datasheet - Page 5
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ADUM5201ARWZ
Manufacturer Part Number
ADUM5201ARWZ
Description
DUAL-CHANNEL ISOLATOR W/INTEGRATED DC/DC
Manufacturer
Analog Devices Inc
Series
IsoPower®, iCoupler®r
Specifications of ADUM5201ARWZ
Inputs - Side 1/side 2
1/1
Number Of Channels
2
Isolation Rating
2500Vrms
Voltage - Supply
3.3V, 5V
Data Rate
1Mbps
Propagation Delay
55ns
Output Type
Logic
Package / Case
16-SOIC (0.300", 7.5mm Width)
Operating Temperature
-40°C ~ 105°C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
105C
Package Type
SOIC W
Rad Hardened
No
Supply Current
7mA
Supply Voltage Range
3V To 5.5V
Digital Ic Case Style
SOIC
No. Of Pins
16
Operating Temperature Range
-40°C To +105°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ADUM5201ARWZ
Manufacturer:
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Quantity:
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Evaluation Board User Guide
DATA I/O CONNECTIONS
Side 1 Data I/O
Signals can be provided to the board and routed to the required
input pins through the IO_1C terminal block connector, as
shown in Figure 4. Four channel inputs/outputs can be connected
from IO_1C Pin 3 through IO_1C Pin 6 to the respective A, B,
C, and D channels of the ADuM540x.
Signals from the IO_1C terminal block connector channels can
also be routed to some of the other data lines through the JP1A
and JP1B jumper blocks (these jumper blocks correspond to
BNC Channel A and Channel B, if you populate them). Each
jumper block allows a channel signal from the IO_1C terminal
block to be connected to additional data input lines by configuring
the jumpers. The jumper blocks can also be used to wrap
signals from an iCoupler output back to an input by using the
JP1A or JP1B block to cross-connect inputs and outputs.
A common way to provide signals is with a function generator
through 50 Ω coax cables. The ADuM540x board has a layout
position at IO_1A and IO_1B for adding two BNC connectors,
but these are not provided with the board. You can purchase the
coax cables (Tyco AMP 227699-2) and populate these BNC
connectors. In addition, to have 50 Ω terminations on the board
for the added BNC connectors, a 50 Ω through-hole resistor
should be added at the R1 and R2 positions. It is possible to
route data outputs to this connector as well, but it is not recom-
mended because proper termination is not possible for logic level
signals, and improper termination can cause severe ringing on
the output lines.
The Side 1 I/O structure also includes pull-up/pull-down/load
positions, R7 through R14. Discrete through-hole resistors and
capacitors can be installed at these positions to simulate most
loading conditions or to provide pull-ups for open collector
outputs.
Side 2 Data I/O
Signals can be provided to the board and routed to the required
input pins through the IO_1D terminal block connector, as
shown in Figure 5. It consists of terminal block connections that
operate like the Side 1 structures. The terminal block connections
can also be used to wrap signals from an iCoupler output back
to an input.
In addition to the off-board I/O connections, each data channel
is provided with through-hole connections to the design area.
Rev. A | Page 5 of 8
DESIGN AREA
The design area of the evaluation board is provided to allow
breadboarding of application components such as RS-485 and
CAN transceivers, ADC or DAC components with direct
interconnects. The design area, as shown in Figure 6, accepts
most surface-mount narrow- and wide-body components with
50 mil and 100 mil pitch, as well as narrow- and wide-body
300 mil DIP through-hole devices. These surface-mount discrete
components and jumper wires can be used to complete a wide
variety of circuits.
The design area has convenient connection points to the
primary data path, CHA to CHD, of the iCoupler, as well as
power connections for V
the design area to be routed to the IO_1D terminal block,
remove the 0 Ω resistors for R23 through R26. Note that no
ground plane is provided in the design area.
GND
CHA
CHB
CHC
CHD
V
ISO
ISO
R23
R25
DESIGN AREA
R26
R24
Figure 6. Design Area
ISO
V
and GND
ISO
ISO
CHD
. To allow signals from
CHA
CHB
CHC
Z6
Z7
UG-042
IO_1D
1
8