ADUC847BCP8-3 Analog Devices Inc, ADUC847BCP8-3 Datasheet - Page 66
![IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC](/photos/6/62/66273/505-56-csp_sml.jpg)
ADUC847BCP8-3
Manufacturer Part Number
ADUC847BCP8-3
Description
IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet
1.EVAL-ADUC845QSZ.pdf
(108 pages)
Specifications of ADUC847BCP8-3
Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PSM, PWM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x24b; D/A 1x12b, 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-LFCSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
ADuC845/ADuC847/ADuC848
USING THE SPI INTERFACE
Depending on the configuration of the bits in the SPICON
SFR shown in Table 41, the SPI interface transmits or receives
data in a number of possible modes. Figure 46 shows all
possible ADuC845/ADuC847/ADuC848 SPI configurations
and the timing relationships and synchronization among the
signals involved. Also shown in this figure is the SPI interrupt
bit (ISPI) and how it is triggered at the end of each byte-wide
communication.
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
DATA OUTPUT
SAMPLE INPUT
DATA OUTPUT
(CPOL = 1)
(CPOL = 0)
ISPI FLAG
ISPI FLAG
SCLOCK
SCLOCK
Figure 46. SPI Timing, All Modes
SS
?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
Rev. B | Page 66 of 108
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. Also note that the SS pin is not
used in master mode. If the parts need to assert the SS pin on an
external slave device, a port digital output pin should be used.
In master mode, a byte transmission or reception is initiated by
a byte write to SPIDAT. The hardware automatically generates
eight clock periods via the SCLOCK pin, and the data is
transmitted via MOSI. With each SCLOCK period, a data bit is
also sampled via MISO. After eight clocks, the transmitted byte
is completely transmitted (via MOSI), and the input byte (if
required) is waiting in the input shift register (after being
received via MISO). The ISPI flag is set automatically, and an
interrupt occurs if enabled. The value in the input shift register
is latched into SPIDAT.
SPI Interface—Slave Mode
In slave mode, the SCLOCK is an input. The SS pin must also
be driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In slave mode, a
data bit is transmitted via MISO, and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte is completely transmitted, and the input
byte is waiting in the input shift register. The ISPI flag is set
automatically, and an interrupt occurs, if enabled. The value in
the shift register is latched into SPIDAT only when the trans-
mission/reception of a byte has been completed. The end of
transmission occurs after the eighth clock has been received if
CPHA = 1, or when SS returns high if CPHA = 0.