ADUC841BCPZ62-5 Analog Devices Inc, ADUC841BCPZ62-5 Datasheet - Page 16
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ADUC841BCPZ62-5
Manufacturer Part Number
ADUC841BCPZ62-5
Description
Microconverter 1-cycle Version ADUC831
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet
1.EVAL-ADUC842QS.pdf
(88 pages)
Specifications of ADUC841BCPZ62-5
Core Processor
8052
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, PSM, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC841/ADuC842/ADuC843
FUNCTIONAL DESCRIPTION
8052 INSTRUCTION SET
Table 4 documents the number of clock cycles required for each
instruction. Most instructions are executed in one or two clock
cycles, resulting in a 16 MIPS peak performance when operating
at PLLCON = 00H on the ADuC842/ADuC843. On the ADuC841,
20 MIPS peak performance is possible with a 20 MHz external
crystal.
Table 4. Instructions
Mnemonic
Arithmetic
Logic
ADD A,Rn
ADD A,@Ri
ADD A,dir
ADD A,#data
ADDC A,Rn
ADDC A,@Ri
ADDC A,dir
ADD A,#data
SUBB A,Rn
SUBB A,@Ri
SUBB A,dir
SUBB A,#data
INC A
INC Rn
INC @Ri
INC dir
INC DPTR
DEC A
DEC Rn
DEC @Ri
DEC dir
MUL AB
DIV AB
DA A
ANL A,Rn
ANL A,@Ri
ANL A,dir
ANL A,#data
ANL dir,A
ANL dir,#data
ORL A,Rn
ORL A,@Ri
ORL A,dir
ORL A,#data
ORL dir,A
ORL dir,#data
XRL A,Rn
XRL A,@Ri
XRL A,#data
XRL dir,A
Description
Subtract indirect memory from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment indirect memory
Increment direct byte
Increment data pointer
Decrement A
Decrement register
Decrement indirect memory
Decrement direct byte
Decimal adjust A
AND register to A
AND indirect memory to A
AND direct byte to A
AND immediate to A
AND A to direct byte
AND immediate data to direct byte
OR indirect memory to A
OR immediate to A
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR indirect memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Add register to A
Add indirect memory to A
Add direct byte to A
Add immediate to A
Add register to A with carry
Add indirect memory to A with carry
Add direct byte to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct from A with borrow
Multiply A by B
Divide A by B
OR register to A
OR direct byte to A
OR A to direct byte
Rev. 0 | Page 16 of 88
Bytes
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1
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Cycles
1
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9
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