ADUC816BSZ Analog Devices Inc, ADUC816BSZ Datasheet
ADUC816BSZ
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ADUC816BSZ Summary of contents
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FEATURES High-Resolution Sigma-Delta ADCs Dual 16-Bit Independent ADCs Programmable Gain Front End 16-Bit No Missing Codes, Primary ADC 13-Bit p-p Resolution @ 20 Hz Range 16-Bit p-p Resolution @ 20 Hz, 2.56 V Range Memory 8 Kbytes ...
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FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Parameter ADC SPECIFICATIONS Conversion Rate Primary ADC 2 No Missing Codes Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift 3 Full-Scale Error 4 Gain Error Drift ADC Range Matching Power Supply Rejection (PSR) Common-Mode DC Rejection On AIN ...
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Parameter INTERNAL REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco ANALOG INPUTS/REFERENCE INPUTS Primary ADC 8, 9 Differential Input Voltage Ranges Bipolar Mode (ADC0CON Analog Input ...
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Parameter TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current AIN– Current Initial Tolerance @ 25°C Drift Drift EXCITATION CURRENT SOURCES Output Current Initial Tolerance @ 25°C Drift Initial Current Matching @ 25°C Drift Matching Line Regulation ( Load Regulation Output ...
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Parameter LOGIC OUTPUTS (Not Including XTAL2 Output High Voltage Output Low Voltage OL Floating State Leakage Current Floating State Output Capacitance POWER SUPPLY MONITOR (PSM) AV Trip Point Selection Range DD AV Power Supply ...
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Parameter POWER REQUIREMENTS (continued) Power Supply Currents Normal Mode DV Current DD AV Current DD DV Current DD AV Current DD 16, 17 Power Supply Currents Idle Mode DV Current DD AV Current DD DV Current DD AV Current DD ...
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Parameter CLOCK INPUT (External Clock Driven XTAL1) t XTAL1 Period CK t XTAL1 Width Low CKL t XTAL1 Width High CKH t XTAL1 Rise Time CKR t XTAL1 Fall Time CKF 1/t ADuC816 Core Clock Frequency CORE t ADuC816 Core ...
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Parameter EXTERNAL PROGRAM MEMORY t ALE Pulsewidth LHLL t Address Valid to ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low to Valid Instruction In LLIV ALE Low to PSEN Low t LLPL PSEN Pulsewidth t ...
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Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t RHDX ...
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Parameter EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth t WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX ALE Low to WR Low t LLWL Address Valid to WR Low t AVWL Data Valid ...
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Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock ...
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Parameter 2 I C-COMPATIBLE INTERFACE TIMING t SCLOCK Low Pulsewidth L t SCLOCK High Pulsewidth H t Start Condition Hold Time SHD t Data Setup Time DSU t Data Hold Time DHD t Setup Time for Repeated Start RSU t ...
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Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time ...
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Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time before ...
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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...
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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...
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ADuC816 ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted) A Parameter Ratings AV to AGND −0 DGND −0 AGND −0 ...
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PIN 1 ADuC816 TOP VIEW (Not to Scale 56-Lead MQFP Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 1, 2 56, 1 P1.0/P1.1 P1.0/T2 P1.1/T2EX 3–4, 2–3, P1.2–P1.7 9–12 11–14 P1.2/DAC/IEXC1 P1.3/AIN5/IEXC2 P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 ...
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ADuC816 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 20, 34, 48 22, 36, 51 21, 35, 47 23, 37, 38, 50 DGND 26 SCLOCK 27 MOSI/SDATA 28–31 30–33 P2.0–P2.7 36–39 39–42 (A8–A15) (A16–A23 XTAL1 ...
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REV. A Figure 12. 52-MQFP Block Diagram –21– ADuC816 ...
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MEMORY ORGANIZATION As with all 8051-compatible devices, the ADuC816 has sepa- rate address spaces for Program and Data memory as shown in Figure 13 and Figure 14. If the user applies power or resets the device while the EA pin ...
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Reset initializes the stack pointer to location 07 hex and increments it once to start from locations 08 hex which is also the first regis- ter (R0) of register bank 1. Thus, if one is going to use more than ...
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SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general- purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip ...
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SFR INTERFACE TO THE PRIMARY AND AUXILIARY ADCS Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following pages. ADCSTAT: ADC Status Register. Holds general status of ...
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ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable Bit Name Description 7 --- Reserved for Future Use. ...
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ADC0CON (Primary ADC Control Register) Used to configure the Primary ADC for range, channel selection, external Ref enable, and unipolar or bipolar coding. SFR Address D2H Power-On Default Value 07H Bit Addressable ...
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ADC1CON (Auxiliary ADC Control Register) Used to configure the Auxiliary ADC for channel selection, external Ref enable and unipolar or bipolar coding. It should be noted that the Auxiliary ADC only operates on a fixed input range of ± V ...
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ICON (Current Sources Control Register) Used to control and configure the various excitation and burnout current source options available on-chip. SFR Address D5H Power-On Default Value 00H Bit Addressable Bit Name Description ...
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OF0H/OF0M (Primary ADC Offset Calibration Registers These two 8-bit registers hold the 16-bit offset calibration coefficient for the Primary ADC. These registers are configured at power- on with a factory default value of 8000Hex. However, these bytes will be automatically ...
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PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION OVERVIEW The ADuC816 incorporates two independent sigma-delta ADCs (Primary and Auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain-gauge, pressure trans- ...
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Auxiliary ADC The Auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range 2.5 V THE EXTERNAL ...
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PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables IX, X and XI below show the output rms noise in μV and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the ...
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The absolute input voltage range on the auxiliary ADC is restricted to between AGND – AVDD + 30 mV. The slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals using ...
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Deriving the reference input voltage across an external resistor, as shown in Figure 52, will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN(+) and REFIN(–) pins would not be recommended in ...
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Figures 23 and 24 show the NMR for 50 Hz and 60 Hz across the full range of SF word, i.e dec 255 dec. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 ...
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NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview The ADuC816 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable, code and data memory space. Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based ...
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Using the Flash/EE Program Memory The 8 Kbyte Flash/EE Program Memory array is mapped into the lower 8 Kbytes of the 64 Kbytes program space addressable by the ADuC816, and is used to hold user code in typical applications. The ...
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Serial Safe Mode This mode disables serial download capability on the device. If Serial Safe mode is activated and an attempt is made to reset the part into serial download mode, i.e., RESET asserted and deasserted with PSEN low, the ...
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Flash/EE Memory Timing The typical program/erase times for the Flash/EE Data Memory are: Erase Full Array (640 Bytes) – Erase Single Page (4 Bytes) – Program Page (4 Bytes) – 250 μs Read Page (4 Bytes) ...
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USER INTERFACE TO OTHER ON-CHIP ADuC816 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC816 incorporates ...
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On-Chip PLL The ADuC816 is intended for use with a 32.768 kHz watch crys- tal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this ...
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Time Interval Counter (TIC) A time interval counter is provided on-chip for counting longer intervals than the standard 8051-compatible timers are capable of. The TIC is capable of timeout intervals ranging from 1/128th second to 255 hours. Furthermore, this counter ...
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TIMECON TIC CONTROL REGISTER SFR Address A1H Power-On Default Value 00H Bit Addressable Bit Name Description 7 --- Reserved for Future Use. 6 --- Reserved for Future Use. For future product code ...
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INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) bit is ...
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Watchdog Timer The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC816 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The ...
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Power Supply Monitor As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC816. It will indicate when any of the supply pins drop below one of four user-selectable voltage trip points ...
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SERIAL PERIPHERAL INTERFACE The ADuC816 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry standard syn- chronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. ...
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Table XIX. SPICON SFR Bit Designations (continued) Bit Name Description 1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit-rate) in Master Mode as follows: SPR1 SPI Slave Mode, i.e., ...
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I C-COMPATIBLE INTERFACE The ADuC816 supports a 2-wire serial interface mode which compatible. The I C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or ...
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ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary periph- eral circuits are also available to the user on-chip. These remaining functions are fully 8051-compatible and are controlled via standard 8051 SFR bit definitions. Parallel I/O ...
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User configuration and control of all Timer operating modes is achieved via three SFRs namely: TMOD, TCON: Control and configuration for Timers 0 and 1. T2CON: Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register SFR ...
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TCON: Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes NOTE These bits are not used in the control of timer/counter 0 and 1, but are used ...
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TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for timer/ counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer ...
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T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag. 6 EXF2 Timer 2 External Flag. EXEN2 = ...
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Timer/Counter 2 Operating Modes The following paragraphs describe the operating modes for timer/ counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXVI. Table XXVI. TIMECON SFR Bit Designations RCLK (or) TCLK ...
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UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive ...
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Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted or ...
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Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: /32) × ...
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INTERRUPT SYSTEM The ADuC816 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: Interrupt Enable Register. IP: Interrupt Priority Register. IEIP2: Secondary ...
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IEIP2: Secondary Interrupt Enable and Priority Register SFR Address A9H Power-On Default Value A0H Bit Addressable Bit Name Description 7 --- Reserved for Future Use. 6 PTI Written by User to Select ...
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ADuC816 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADuC816 into any hardware system. Clock Oscillator As described earlier, the core clock frequency for the ADuC816 is ...
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ADuC816 P0 LATCH ALE P2 LATCH either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer (DPL address, which is latched by a pulse of ...
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As an alternative to providing two separate power supplies, AV quiet by placing a small series resistor and/or ferrite bead between it and DV , and then decoupling example of this configuration is shown in Figure 50. ...
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PLACE ANALOG A COMPONENTS HERE AGND PLACE ANALOG B COMPONENTS HERE AGND PLACE ANALOG C COMPONENTS HERE GND In all of these scenarios, and in more complicated real-life appli- cations, keep in mind the flow of current from the supplies ...
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AV DD 200 A/400 A EXCITATION CURRENT V + REF R1 V – 5.6k REF RTD A – 510 DVDD ADM810 V RST CC GND ADM202 C1+ V+ C1– C2+ C2– V– T2OUT R2IN comes ...
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It should also be noted that variations in the excitation current do not affect the measurement system, as the input voltage from the RTD and reference voltage across R1 vary ratiometrically with the excitation current. Resistor R1 must, however, have ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADuC816BSZ –40°C to +85°C ADuC816BSZ-REEL –40°C to +85°C ADuC816BCPZ –40°C to +85°C ADuC816BCPZ-REEL –40°C to +85° RoHS Compliant Part. ©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...