ADUC7122BBCZ Analog Devices Inc, ADUC7122BBCZ Datasheet - Page 72

• Manufacturer Part Number: ADUC7122BBCZ
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7122BBCZ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x12b, D/A 12x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7122
Bit
8
7
6
5
4
3
2
1
0
Name
SPIROW
SPIZEN
SPITMDE
SPILF
SPIWOM
SPICPO
SPICPH
SPIMEN
SPIEN
SPIRX overflow overwrite enable.
SPI transmit zeros when the Tx FIFO is empty.
SPI transfer and interrupt mode.
LSB first transfer enable bit.
Serial clock polarity mode bit.
Serial clock phase mode bit.
Master mode enable bit.
SPI enable bit.
Description
Set by the user, the valid data in the Rx register is overwritten by the new serial byte received.
Cleared by the user, the new serial byte received is discarded.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
Set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.
Set by the user, the LSB is transmitted first
Cleared by the user, the MSB is transmitted first.
SPI wired or mode enable bit
Set to 1 to enable open-drain data output enable. External pull-ups required on data out pins.
Cleared for normal output levels.
Set by the user, the serial clock idles high.
Cleared by the user, the serial clock idles low.
Set by the user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user, the serial clock pulses at the end of each serial bit transfer.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
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