ADUC7023BCP6Z62I Analog Devices Inc, ADUC7023BCP6Z62I Datasheet - Page 32

• Manufacturer Part Number: ADUC7023BCP6Z62I
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCP6Z62I

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12 x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
ADCGN Register
Name:
Address:
Default value:
Access:
Function:
ADCOF Register
Name:
Address:
Default value:
Access:
Function:
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three different modes: differential,
pseudo differential, and single-ended.
Differential Mode
The ADuC7023 contains a successive approximation ADC
based on two capacitive DACs. Figure 23 and Figure 24 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC is comprised of control logic, a
SAR, and two capacitive DACs. In Figure 23 (the acquisition
phase), SW3 is closed and SW1 and SW2 are in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
ADC11
ADC0
MUX
CHANNEL+
CHANNEL–
ADCGN
Factory configured
Read/write
register.
ADCOF
Factory configured
Read/write
ADCOF is a 10-bit offset calibration
register.
0xFFFF0530
ADCGN is a 10-bit gain calibration
0xFFFF0534
B
A
A
B
V
REF
SW1
SW2
C
C
S
S
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC
Rev. B | Page 32 of 96
ADC11
When the ADC starts a conversion, as shown in Figure 24,
SW3 opens, and then SW1 and SW2 move to Position B. This
causes the comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The control logic
and the charge redistribution DACs are used to add and
subtract fixed amounts of charge from the sampling capacitor
arrays to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code. The output
impedances of the sources driving the V
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
ADC11
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the V
of the ADuC7023 SW2 switches between A (Channel−) and B
(V
The input signal on V
V
AIN11
ADC0
ADC0
AIN0
V
IN−
V
IN–
REF
IN–
must be chosen so that V
). V
MUX
MUX
MUX
IN−
pin must be connected to ground or a low voltage.
CHANNEL+
CHANNEL–
CHANNEL+
CHANNEL–
CHANNEL+
CHANNEL–
Figure 25. ADC in Pseudo Differential Mode
Figure 23. ADC Acquisition Phase
Figure 24. ADC Conversion Phase
IN+
B
A
A
B
B
A
A
B
V
V
B
A
A
B
V
REF
REF
SW1
SW2
SW1
SW2
REF
SW1
SW2
can then vary from V
C
C
C
C
REF
C
C
S
S
S
S
S
S
+ V
IN−
SW3
SW3
SW3
does not exceed AV
IN+
COMPARATOR
COMPARATOR
COMPARATOR
and V
IN−
IN–
to V
pins must
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
REF
CONTROL
CONTROL
CAPACITIVE
CAPACITIVE
DAC
LOGIC
DAC
DAC
LOGIC
DAC
IN−
+ V
CONTROL
DAC
LOGIC
DAC
DD
pin
IN−
.
.