ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 21

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8
register. Set this register prior to using the TWI port.
Table 8. TWI_DT Field Selections and V
Clock Related Operating Conditions
Table 9
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 10
Table 9. Core Clock (CCLK) Requirements
Table 10. Phase-Locked Loop Operating Conditions
1
Table 11. SCLK Conditions
1
Parameter
f
Parameter
f
f
TWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)
Parameter
f
For more information, see Ordering Guide on Page 65.
f
VCO
SCLK
SCLK
CCLK
SCLK
must be less than or equal to f
shows settings for TWI_DT in the NONGPIO_DRIVE
describes the timing requirements for the processor
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
describes phase-locked loop operating conditions.
1
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Voltage Controlled Oscillator (VCO) Frequency
(Commercial/Industrial Models)
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
CLKOUT/SCLK Frequency (V
Minimum)
CLKOUT/SCLK Frequency (V
V
3.3
1.8
2.5
1.8
3.3
1.8
2.5
—
DDEXT
CCLK
and is subject to additional restrictions for SDRAM interface operation. See
Nominal
DDINT
DDINT
DDINT
DDINT
DDEXT
DDINT
DDINT
=1.23 V Minimum, Industrial/Commercial Models)
=1.33 V Minimum, All Models)
= 1.14 V Minimum, Industrial Models Only)
= 1.10 V Minimum, Commercial Models Only)
≥ 1.230 V
< 1.230 V)
/V
BUSTWI
Rev. B | Page 21 of 68 | January 2011
V
2.97
1.7
2.97
2.97
4.5
2.25
2.25
—
BUSTWI
Minimum
V
1.8 V Nominal
80
80
Max
DDEXT
/V
DDMEM
V
3.3
1.8
3.3
3.3
5
2.5
2.5
—
BUSTWI
Nominal
Min
Table 28 on Page
V
Max
100
80
72
84
Voltage Setting
2.5 V or 3.3 V Nominal
DDEXT
Nominal
/V
1.200 V
1.150 V
1.400 V
1.300 V
DDMEM
Max
V
3.63
1.98
3.63
3.63
5.5
2.75
2.75
—
31.
BUSTWI
Instruction Rate
Instruction Rate
Maximum
Maximum
200
200
400
300
1
1
Unit
MHz
MHz
Unit
MHz
MHz
Unit
MHz
MHz
MHz
MHz
Unit
V
V
V
V
V
V
V
—