ADSP-BF512KSWZ-3 Analog Devices Inc, ADSP-BF512KSWZ-3 Datasheet - Page 48

• Manufacturer Part Number: ADSP-BF512KSWZ-3
• Description: Low-Power Blackfin Processor
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF512KSWZ-3

• Interface: I²C, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 47. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
1
2
Table 48. 10/100 Ethernet MAC Controller Timing: MII Station Management
1
Parameter
Timing Requirements
t
t
t
t
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
ECOLH
ECOLL
ECRSH
ECRSL
MDIOS
MDCIH
MDCOV
MDCOH
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
of the system clock SCLK. MDIO is a bidirectional data line.
1
COL Pulse Width High
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
MDIO (OUTPUT)
MDC (OUTPUT)
MDIO (INPUT)
MIICRS, COL
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Station Management
2
1
Figure 35. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
2
1
Rev. B | Page 48 of 68 | January 2011
t
t
ECRSH
ECOLH
t
MDCOH
t
MDCOV
t
MDIOS
t
t
ECRSL
ECOLL
Min
t
t
t
t
t
t
t
ETxCLK
ERxCLK
ETxCLK
ERxCLK
ETxCLK
ETxCLK
MDCIH
× 1.5
× 1.5
× 1.5
× 1.5
× 1.5
× 1.5
Min
11.5
0
–1.25
Max
Max
25
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns