ADSP-2191MBSTZ-140 Analog Devices Inc, ADSP-2191MBSTZ-140 Datasheet - Page 29

• Manufacturer Part Number: ADSP-2191MBSTZ-140
• Description: IC,DSP,16-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2191MBSTZ-140

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 140MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Clock Freq (max): 140MHz
• Mips: 140
• Device Input Clock Speed: 140MHz
• Ram Size: 160KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/2.97V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2191MBSTZ140

Host Port ALE Mode Read Cycle Timing
Table 17
Address Latch Enable (ALE) mode. For more information on
ACK, Ready, ALE, and ACC mode selection, see the Host port
modes description
Table 17. Host Port ALE Mode Read Cycle Timing
1
2
REV. A
t
Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
NH
Parameter
Switching Characteristics
t
t
t
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
the same time.
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
RHKS1
RHKS2
RHKH
RHS
RHH
RDH
RDD
CSAL
ALCS
RCSW
ALR
RCS
ALPW
HKRD
AALS
ALAH
are peripheral bus latencies (n t
and
Figure 16
HRD Asserted to HACK Asserted (ACK Mode) First Byte
HRD Asserted to HACK Asserted (Setup, ACK Mode)
HRD Deasserted to HACK Deasserted (Hold, ACK Mode)
HRD Asserted to HACK Asserted (Setup, Ready Mode)
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
HRD Deasserted to Data Invalid (Hold)
HRD Deasserted to Data Disable
HCMS or HCIOMS Asserted to HALE Asserted (Delay)
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
HRD Deasserted to HCMS or HCIOMS Deasserted
HALE Deasserted to HRD Asserted
HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)
HALE Asserted Pulsewidth
HACK Asserted to HRD Deasserted (Hold, ACK Mode)
Address Valid to HALE Deasserted (Setup)
HALE Deasserted to Address Invalid (Hold)
on Page
describe Host port read operations in
8.
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
–29–
2
Min
12t
12t
1
0
1
0
5
0
4
1.5
2
4
HCLK
HCLK
ADSP-2191M
Max
15t
12
10
10
15t
10
HCLK
HCLK
+t
+t
NH
NH
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns