ADSP-2184LBSTZ-160 Analog Devices Inc, ADSP-2184LBSTZ-160 Datasheet - Page 25

• Manufacturer Part Number: ADSP-2184LBSTZ-160
• Description: 3.3V 16Bit DSP,40mips,4kWrdsPM/DM,100TQF
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2184LBSTZ-160

• Interface: Host Interface, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bus Request–Bus Grant
Table 16. Bus Request—Bus Grant
1
2
3
4
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the
xMS = PMS, DMS, CMS, IOMS, BMS.
For the ADSP-2187L, this specification is 0.25t
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
BR Hold After CLKOUT High
BR Setup Before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
PMS, DMS
CMS, WR,
BMS, RD
CLKOUT
CLKOUT
IOMS
BGH
BG
BR
CK
– 4 ns min.
1
1
t
SD
t
4
4
BH
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 25 of 48 | January 2008
Figure 18. Bus Request—Bus Grant
t
t
3
BS
t
SDBH
2
SDB
Min
0.25t
0.25t
0
0
0.25t
0
0
t
t
SEH
SE
CK
CK
CK
t
SEC
+ 2
+ 17
– 7
Max
0.25t
CK
+ 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns