ADSP-21469BBCZ-3 Analog Devices Inc, ADSP-21469BBCZ-3 Datasheet - Page 46

• Manufacturer Part Number: ADSP-21469BBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469BBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
Sample Rate Converter—Serial Output Port
For the serial output port, the frame sync is an input and it
should meet setup and hold times with regard to the serial clock
on the output port. The serial data output has a hold time and
Table 42. ASRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
SRCSFS
SRCHFS
SRCCLKW
SRCCLK
SRCTDD
SRCTDH
can be either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Clock Width
Clock Period
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(SCLK)
(FS)
t
SRCTDH
Figure 31. ASRC Serial Output Port Timing
t
Rev. 0 | Page 46 of 72 | June 2010
SRCTDD
t
SRCCLKW
t
SRCSFS
SAMPLE EDGE
delay specification with regard to serial clock. Note that the
serial clock rising edge is the sampling edge, and the falling edge
is the drive edge.
t
SRCHFS
t
SRCCLK
Min
4
5.5
(t
t
1
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
9.9
Unit
ns
ns
ns
ns
ns
ns