ADSP-21369KBPZ-2A Analog Devices Inc, ADSP-21369KBPZ-2A Datasheet - Page 20

• Manufacturer Part Number: ADSP-21369KBPZ-2A
• Description: IC,DSP,32-BIT,CMOS,BGA,256PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KBPZ-2A

• Interface: DAI, DPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA Exposed Pad, 256-eBGA, 256-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21367/ADSP-21368/ADSP-21369
Power-Up Sequencing
The timing requirements for processor start-up are given in
Table
approximately 200μA may be observed on the RESET pin if it is
Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up)
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
default states at all I/O pins.
maximum.
1
12. Note that during power-up, a leakage current of
DDINT
/V
DDEXT
CLK_CFG1–0
RESETOUT
assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
RESET
V
V
CLKIN
DDINT
DDEXT
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
DDINT
srst
On Before V
specification in
t
RSTVDD
DDEXT
Table
DDINT
DDINT
/V
t
/V
IVDDEVDD
14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles
DDEXT
DDEXT
Valid
Rev. E | Page 20 of 60 | July 2009
On
Figure 6. Power-Up Sequencing
t
CLKVDD
t
PLLRST
t
CLKRST
driven low before power up is complete. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Min
0
–50
0
10
20
4096t
t
2
CORERST
CK
+ 2 t
CCLK
3, 4
Max
+200
200
Unit
ns
ms
ms
μs
μs