ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 35

ADSP-21065L 60 Mhz

ADSP-21065LCSZ-240

Manufacturer Part Number
ADSP-21065LCSZ-240
Description
ADSP-21065L 60 Mhz
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21065LCSZ-240

Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
60MHz
Mips
60
Device Input Clock Speed
60MHz
Ram Size
68KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADS-P21065LCSZ240
ADS-P21065LCSZ240

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
AD
Quantity:
310
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
Analog Devices Inc
Quantity:
10 000
JTAG Test Access Port and Emulation
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
NOTES
1
2
REV. C
System Inputs = DATA
System Outputs = DATA
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BSEL, BMS, CLKIN, RESET, SDCLK
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, SDCLK0, SDCLK1, DQM, SDA10, RAS, CAS, SDWE, SDCKE, BM, XTAL.
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth
TDO Delay from TCK Low
System Outputs Delay After TCK Low
31-0
31-0
OUTPUTS
, ADDR
SYSTEM
SYSTEM
, ADDR
INPUTS
TMS
TDO
TCK
TDI
23-0
23-0
, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR
, MS
3-0
, RD, WR, ACK, SW, HBG, REDY, DMAG1
Figure 23. JTAG Test Access Port and Emulation
t
DTDO
1
t
t
STAP
DSYS
1
2
–35–
t
t
TCK
HTAP
1
,
, DMAR
Min
t
3.0
3.0
7.0
12.0
4 t
DMAG2, BR
CK
0
, RAS, CAS, SDWE, SDCKE, PWM_EVENTx.
CK
2
t
, BR
SSYS
2-1
2-1
, CPA, FLAG
, ID
1-0
, IRQ
2-0
t
HSYS
11-0
, FLAG
, PWM_EVENTx, DT0x, DT1x,
Max
15.0
11.0
11-0
ADSP-21065L
, DR0x, DR1x, TCLK0,
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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