ADSP-21062KS-160 Analog Devices Inc, ADSP-21062KS-160 Datasheet - Page 26

• Manufacturer Part Number: ADSP-21062KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21062KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 2M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Package: 240MQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 256 KB
• Device Million Instructions Per Second: 40 MIPS

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
Table 15. Memory Write—Bus Master
1
2
3
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
HI = t
I = t
ACK is not sampled on external memory accesses that use the internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be valid by
The falling edge of MSx, SW, BMS is referenced.
See
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
DDWR
WDE
SADADC
t
of a wait stated external memory access, synchronous specifications t
states have completed).
DAAK
Example System Hold Time Calculation on Page 48
CK
CK
CK
or t
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
DSAK
or synchronous specification t
ACK Delay from Address, Selects
ACK Delay from WR Low
Address Selects to WR Deasserted
Address Selects to WR Low
WR Pulse Width
Data Setup Before WR High
Address Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
Address, Selects Setup Before ADRCLK High
SACKC
1
2
for wait state modes external, either, or both (both, if the internal wait state is zero). For the second and subsequent cycles
for calculation of hold times given capacitive and dc loads.
1, 2
3
2
Rev. G | Page 26 of 64 | August 2010
SACKC
CK
2
.
and t
HACK
must be met for wait state modes external, either, or both (both, after internal wait
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Min
17 + 15DT/16 + W
3 + 3DT/8
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 +H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
5 V and 3.3 V
Max
14 + 7DT/8 + W
8 + DT/2 + W
6 + DT/16+H
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns