ADSP-21060LKSZ-160 Analog Devices Inc, ADSP-21060LKSZ-160 Datasheet - Page 30
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ADSP-21060LKSZ-160
Manufacturer Part Number
ADSP-21060LKSZ-160
Description
IC,DSP,32-BIT,CMOS,QFP,240PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Specifications of ADSP-21060LKSZ-160
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
240-MQFP, 240-PQFP
Device Core Size
32b
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
512KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21060LKSZ-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106xs (BRx) or a host processor, both
synchronous and asynchronous (HBR, HBG).
Table 18. Multiprocessor Bus Request and Host Bus Request
1
2
3
4
5
6
7
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t
Only required for recognition in the current cycle.
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
For ADSP-21060LC, specification is 8.5 – DT/8 ns max.
For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max.
(O/D) = open drain, (A/D) = active drive.
For ADSP-21060C/ADSP-21060LC, specification is 40 + 23DT/16 ns min.
HBGRCSV
SHBRI
HHBRI
SHBGI
HHBGI
SBRI
HBRI
SRPBAI
HRPBAI
DHBGO
HHBGO
DBRO
HBRO
DCPAO
TRCPA
DRDYCS
TRDYHG
ARDYTR
easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC
User’s Manual, Revision 2.1.
HBG Low to RD/WR/CS Valid
HBR Setup Before CLKIN
HBR Hold After CLKIN
HBG Setup Before CLKIN
HBG Hold After CLKIN High
BRx, CPA Setup Before CLKIN
BRx, CPA Hold After CLKIN High
RPBA Setup Before CLKIN
RPBA Hold After CLKIN
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS and HBR Low
REDY (O/D) Disable or REDY (A/D) High from HBG
REDY (A/D) Disable from CS or HBR High
2
2
4
1
3
Rev. F | Page 30 of 64 | March 2008
6
5, 6
6, 7
CK
before RD or WR goes low or by t
Min
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
–2 – DT/8
–2 – DT/8
–2 – DT/8
44 + 23DT/16
5 V and 3.3 V
HBGRCSV
Max
20 + 5DT/4
14 + 3DT/4
6 + DT/2
6 + DT/2
12 + 3DT/4
7 – DT/8
7 – DT/8
8 – DT/8
4.5 – DT/8
8.5
10
after HBG goes low. This is
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns