ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 18

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN8102
Table 8. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps)
EQ_A[1:0] and
EQ_B[1:0] Pins
0
1
2
3
1
Table 9. Receive Configuration and Equalization Registers
Name
IN_A/IN_B
configuration
IN_A/IN_B
EQ1 control
IN_A/IN_B
EQ2 control
IN_Ax/IN_Bx
FR4 control
Loss of Signal/Signal Detect
An independent signal detect output is provided for all eight
input ports of the device. The signal-detect function measures
the low frequency amplitude of the signal at the receiver input
and compares this measurement with a defined threshold level.
If the measurement indicates that the input signal swing is
smaller than the threshold for 250 μs, the channel indicates a
loss-of-signal event. Assertion and deassertion of the LOS signal
occurs within 100 μs of the event.
The LOS-assert and LOS-deassert levels are set on a per channel
basis through the I
IN_B LOS threshold and IN_A/IN_B LOS hysteresis registers,
respectively. The recommended settings are IN_A/IN_B LOS
threshold = 0x0C and IN_A/IN_B LOS hysteresis = 0x0D.
All ports are factory tested with these settings to ensure that an
LOS event is asserted for single-ended dc input swings less than
20 mV and is deasserted for single-ended dc input swings greater
than 225 mV.
The LOS status for each individual channel can be accessed
through the I
LOS status can be read from the IN_A/IN_B LOS status registers
(Address 0x1F and Address 0x3F). The four LSBs of each register
represent the current LOS status of each channel, with high
representing an ongoing LOS event. The four MSBs of each
X = Don’t care
2
C control interface. The independent channel
Address
0x80, 0xA0
0x83, 0xA3
0x84, 0xA4
0x85, 0x8D, 0x95,
0x9D, 0xA5, 0xAD,
0xB5, 0xBD
2
C control interface, by writing to the IN_A/
IN_Ax/IN_Bx
Configuration,
EQ[2:0]
X
0
1
2
3
4
5
6
7
1
Bit 7
EQBY
1
0
0
0
0
0
0
0
0
Bit 6
PNSWAP
EQ CTL SRC
Boost (dB)
1.5
10
12
14
17
19
20
21
22
Bit 5
EQBY
EQ1[5]
EQ2[5]
Rev. B | Page 18 of 36
Cable Optimized
Bit 4
EN
EQ1[4]
EQ2[4]
Typical CX4 Cable
Length (Meters)
< 2
2 to 6
8 to 10
12 to 14
16 to 18
20 to 22
24 to 26
28 to 30
30 to 32
register represent the historical LOS status of each channel,
with high representing a LOS event at any time on a specific
channel. The MSBs are sticky and remain high once asserted
until cleared by the user by overwriting the bits to 0.
Recommended LOS Settings
Recommended settings for LOS are as follows:
•
•
LANE INVERSION
The input P/N inversion is a feature intended to allow the user
to implement the equivalent of a board-level crossover in a much
smaller area and without additional via impedance discontinuities
that degrade the high frequency integrity of the signal path. The
P/N inversion is available on a per port basis and is controlled
through the I
plished by writing to the PNSWAP bit (Bit 6) of the IN_A/IN_B
configuration register (see Table 9) with low representing a
noninverting configuration and high representing an inverting
configuration. Note that using this feature to account for signal
inversions downstream of the receiver requires additional attention
when switching connectivity.
Set IN_A/IN_B LOS threshold to 0x0C for an assert
voltage of 20 mV differential (40 mV p-p differential).
Set IN_A/IN_B LOS hysteresis to 0x0D for a deassert voltage
of 225 mV differential (450 mV p-p differential).
Bit 3
EQ1[3]
EQ2[3]
2
C control interface. The P/N inversion is accom-
Bit 2
EQ[2]
EQ1[2]
EQ2[2]
1.5
Boost (dB)
3.5
3.9
4.25
4.5
4.75
5.0
5.3
5.5
Bit 1
EQ[1]
EQ1[1]
EQ2[1]
LUT SELECT
FR4 Optimized
Bit 0
EQ[0]
EQ1[0]
EQ2[0]
LUT FR4/CX4
Typical FR4 Trace
Length (Inches)
< 5
5 to 10
10 to 15
15 to 20
20 to 25
25 to 30
30 to 35
35 to 40
35 to 40
Default
0x30
0x00
0x00
0x00