ADN2811ACPZ-CML Analog Devices Inc, ADN2811ACPZ-CML Datasheet - Page 11

• Manufacturer Part Number: ADN2811ACPZ-CML
• Description: S/Rate 2.5/2.7Gbps CDR/ PA Low Power I.C
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2811ACPZ-CML

• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Input: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. Jitter accommodation is roughly
0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed-loop bandwidth
of the delay-locked loop, which is roughly 5 MHz.
Rev. B | Page 11 of 20
JITTER
GAIN
(dB)
Figure 13. Jitter Response vs. Conventional PLL
n psh
o
d psh
JITTER PEAKING
IN ORDINARY PLL
c
ADN2811
Z(s)
X(s)
ADN2811
f
(kHz)