ADM8690ARN Analog Devices Inc, ADM8690ARN Datasheet - Page 11

• Manufacturer Part Number: ADM8690ARN
• Description: IMPROVED ADM690
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM8690ARN

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)

In addition to RESET , the ADM8691/ADM8693/ADM8695
contain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
reset signal.
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop. An
output line on the processor is used to toggle the watchdog input
(WDI) line. If this line is not toggled within the selected timeout
period, a RESET pulse is generated. The nominal watchdog
timeout period is preset at 1.6 seconds on the ADM8690/
ADM8692/ADM8694. The ADM8691/ADM8693/ADM8695
can be configured for either a fixed short 100 ms, or a long
1.6 second timeout period, or for an adjustable timeout period. If
the short period is selected, some systems are unable to service
the watchdog timer immediately after a reset, so the ADM8691/
ADM8693/ADM8695 automatically select the long timeout
period directly after a reset is issued. The watchdog timer is
restarted at the end of reset, whether the reset was caused by
lack of activity on WDI or by V
threshold.
Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
Low
Low
Floating or high
Floating or high
1
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F
1
1
OSC IN
External clock input
External capacitor
Low
Floating or high
CC
falling below the reset
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
Normal
1024 CLKs
400 ms × C/47 pF
100 ms
1.6 s
Watchdog Timeout Period
Rev. A | Page 11 of 20
Immediately After Reset
4096 CLKs
1.6 s × C/47 pF
1.6 s
1.6 s
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at, or less than, the minimum timeout period. If
WDI remains permanently either high or low, reset pulses are
issued after each long (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the watchdog input
(WDI) or by connecting it to midsupply.
RESET
WDO
WDI
t
t
t
1
2
3
= RESET TIME
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
Figure 16. Watchdog Timeout Period and Reset Active Time
OSC
t
1
(Hz) = 184,000/C (pF).
ADM8691/ADM8693
512 CLKs
200 ms × C/47 pF
50 ms
50 ms
t
2
t
1
Reset Active Period
t
3
ADM8695
2048 CLKs
520 ms × C/47 pF
200 ms
200 ms
t
1