ADM823RYRJZ-R7 Analog Devices Inc, ADM823RYRJZ-R7 Datasheet - Page 9

• Manufacturer Part Number: ADM823RYRJZ-R7
• Description: IC,Power Supply Supervisor,TSOP,5PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Simple Reset/Power-On Resetr

Specifications of ADM823RYRJZ-R7

• Package / Case: SOT-23-5, SC-74A, SOT-25
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Number Of Voltages Monitored: 1
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.63V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CIRCUIT DESCRIPTION
The ADM823/ADM824/ADM825 provide microprocessor
supply voltage supervision by controlling the microprocessor’s
reset input. Code-execution errors are avoided during power-
up, power-down, and brownout conditions by asserting a reset
signal when the supply voltage is below a preset threshold. They
are also avoided by allowing supply voltage stabilization with a
fixed-timeout reset pulse after the supply voltage rises above the
threshold. In addition, problems with microprocessor code
execution can be monitored and corrected with a watchdog
timer (ADM823/ ADM824). By including watchdog strobe
instructions in microprocessor code, a watchdog timer can detect
if the microprocessor code breaks down or becomes stuck in an
infinite loop. If this happens, the watchdog timer asserts a reset
pulse that restarts the microprocessor in a known state. If the
user detects a problem with the system’s operation, a manual
reset input is available (ADM823/ADM825) to reset the
microprocessor with an external push-button, for example.
RESET OUTPUT
The ADM823 features an active-low, push-pull reset output
while the ADM824/ADM825 feature dual active-low and
active-high push-pull reset outputs. For active-low and active-
high outputs, the reset signal is guaranteed to be logic low and
logic high, respectively, for V
The reset output is asserted when V
threshold (V
serviced within the watchdog timeout period (t
remains asserted for the duration of the reset active timeout
period (t
transitions from low-to-high, or after the watchdog timer times
out. Figure 15 illustrates the behavior of the reset outputs.
RESET
RESET
V
CC
RP
V
V
V
) after V
1V
1V
0V
0V
0V
CC
CC
CC
TH
), when MR is driven low, or when WDI is not
Figure 15. Reset Timing Diagram
CC
V
rises above the reset threshold, after MR
TH
t
t
RP
RP
CC
down to 1 V.
CC
is below the reset
t
RD
WD
V
TH
). Reset
t
RD
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MANUAL RESET INPUT
The ADM823/ADM825 feature a manual reset input ( MR )
which, when driven low, asserts the reset output. When MR
transitions from low to high, reset remains asserted for the
duration of the reset active timeout period before deasserting.
The MR input has a 52 kV internal pull-up so that the input is
always high when unconnected. An external push-button
switch can be connected between MR and ground so that the
user can generate a reset. Debounce circuitry for this purpose is
integrated on-chip. Noise immunity is provided on the MR
input and fast, negative-going transients of up to 100 ns (typ)
are ignored. A 0.1 µF capacitor between MR and ground
provides additional noise immunity.
WATCHDOG INPUT
The ADM823/ADM824 feature a watchdog timer which
monitors microprocessor activity. A timer circuit is cleared with
every low-to-high or high-to-low logic transition on the watch-
dog input pin (WDI), which detects pulses as short as 50 ns. If
the timer counts through the preset watchdog timeout period
(t
the WDI pin to avoid being reset. Failure of the microprocessor
to toggle WDI within the timeout period therefore indicates a
code execution error, and the reset pulse generated restarts the
microprocessor in a known state.
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condi-
tion on V
the watchdog timer is cleared and does not begin counting
again until reset deassserts. The watchdog timer can be disabled
by leaving WDI floating or by three-stating the WDI driver.
WD
RESET
), reset is asserted. The microprocessor is required to toggle
WDI
V
CC
CC
V
V
V
1V
0V
0V
0V
CC
CC
CC
or by MR being pulled low. When reset is asserted,
Figure 16. Watchdog Timing Diagram
V
t
RP
TH
ADM823/ADM824/ADM825
t
WD
t
RD